公开(公告)号：WO2022086703A1

公开(公告)日：2022-04-28

申请号：PCT/US2021/053590

申请日：2021-10-05

Applicant: RAMBUS INC.

Inventor： KELLAM, Mark D.

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing. The wavelength of the light is selected such that the photons impinging on the flash memory cell have an energy that approaches the barrier height (conduction band offset) of the tunnel insulator. Illuminating the flash memory cell during programming/erase increases the tunneling current through the tunnel insulator by way of the photon assisted tunneling (PAT) effect.

公开(公告)号：WO2008067494A1

公开(公告)日：2008-06-05

申请号：PCT/US2007/085979

申请日：2007-11-29

Applicant: RAMBUS INC. ,  BRONNER, Gary ,  HAUKNESS, Brent S. ,  ASSADERAGHI, Fariborz ,  KELLAM, Mark D. ,  HOROWITZ, Mark

Inventor： BRONNER, Gary ,  HAUKNESS, Brent S. ,  ASSADERAGHI, Fariborz ,  KELLAM, Mark D. ,  HOROWITZ, Mark

IPC: H01L23/34 ,  H01L21/8247 ,  H01L27/105 ,  H05B3/14 ,  H01L21/00

CPC classification number: H01L27/105 ,  H01L21/67103 ,  H01L23/345 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).

Abstract translation: 集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。 存储器件的字线或位线用作加热元件（107）。

公开(公告)号：WO2011056281A1

公开(公告)日：2011-05-12

申请号：PCT/US2010/046831

申请日：2010-08-26

Applicant: RAMBUS INC. ,  KELLAM, Mark D. ,  BRONNER, Gary B.

Inventor： KELLAM, Mark D. ,  BRONNER, Gary B.

IPC: G11C5/02 ,  G11C7/18 ,  G11C8/14 ,  H01L27/115

CPC classification number: G11C5/063 ,  G11C5/02 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146

Abstract: A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.

Abstract translation: 存储装置包括平面基板，平面基板上方的多个水平导电平面以及与多个水平导电平面交错的多个水平绝缘层。 垂直于多个导电平面和绝缘层的垂直导电柱阵列穿过多个导电平面和绝缘层中的孔。 存储器件包括多个可编程存储器元件，每个可编程存储器元件将一个水平导电平面耦合到相应的垂直导电柱。

公开(公告)号：WO2009017871A1

公开(公告)日：2009-02-05

申请号：PCT/US2008/064246

申请日：2008-05-20

Applicant: RAMBUS INC. ,  KELLAM, Mark D.

Inventor： KELLAM, Mark D.

IPC: H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7883 ,  H01L29/0649 ,  H01L29/512 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region.

Abstract translation: 晶体管包括具有表面的衬底，其中衬底的第一区域和第二区域掺杂有第一类型的掺杂剂，并且其中第一区域和第二区域之间的衬底的第三区域掺杂有第二区域 掺杂剂类型。 在包括第三区域的表面的一部分上方沉积绝缘体层，并且在绝缘体层上方沉积栅极层。 封装层封闭栅极层的端部，从而在绝缘体层的端部和封装层之间限定间隙。 这些间隙具有相对于栅极层的端部的深度，绝缘体层的一端靠近第一区域和第三区域之间的边界，绝缘体层的另一端靠近第二区域和第二区域之间的边界 第三区。