公开(公告)号：WO2014008165A3

公开(公告)日：2014-01-09

申请号：PCT/US2013/048883

申请日：2013-07-01

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： PURAYATH, Vinod ,  SAMACHISA, George ,  MATAMIS, George ,  KAI, James ,  ZHANG, Yuan

IPC: H01L29/423 ,  H01L29/788 ,  H01L27/115

Abstract: A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4 x 1012 dots/cm2. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer.

公开(公告)号：WO2014189808A2

公开(公告)日：2014-11-27

申请号：PCT/US2014/038528

申请日：2014-05-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： PURAYATH, Vinod R. ,  KAI, James ,  LEE, Donovan ,  ZHANG, Yuan ,  MATSUDAIRA, Akira

IPC: H01L21/28

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/42324

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract translation: 一种非易失性存储器系统，包括具有在浮动栅极上具有倒T形的字线的非易失性存储装置。 倒T形形状具有较宽的底部部分和更薄的顶部部分。 较薄的顶部部分相对于较宽底部之间的间隔增加了相邻字线之间的间隔。 气隙可以分开相邻的字线。 字线的较薄顶部增加了相邻字线之间的路径长度。 可以通过减少相邻字线之间的电场来减小字线到字线短路的可能性。

公开(公告)号：WO2012003301A2

公开(公告)日：2012-01-05

申请号：PCT/US2011/042566

申请日：2011-06-30

Applicant: SANDISK TECHNOLOGIES INC. ,  ALSMEIER, Johann ,  PURAYATH, Vinod ,  CHIEN, Henry ,  MATAMIS, George ,  LEE, Yao-Sheng ,  KAI, James ,  ZHANG, Yuan ,  SAMACHISA, George

Inventor： ALSMEIER, Johann ,  PURAYATH, Vinod ,  CHIEN, Henry ,  MATAMIS, George ,  LEE, Yao-Sheng ,  KAI, James ,  ZHANG, Yuan ,  SAMACHISA, George

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/66833 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/78642 ,  H01L29/7889 ,  H01L29/7926

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Abstract translation: 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：WO2015006152A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/045347

申请日：2014-07-03

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： CHIEN, Henry ,  LEE, Donovan ,  PURAYATH, Vinod R. ,  ZHANG, Yuan ,  KAI, James K. ,  MATAMIS, George

IPC: H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract translation: 一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括电绝缘材料，第二材料包括半导体或导体材料。 该方法还包括蚀刻堆叠以在堆叠中形成前侧开口，在暴露在前侧开口中的第一材料和第二材料的交替层的叠层上形成阻挡电介质层，形成半导体或金属电荷存储 在所述阻挡电介质上方形成在所述电荷存储层上方的隧道介电层，在所述隧道介电层上形成半导体沟道层，蚀刻所述堆叠以在所述堆叠中形成背侧开口，去除所述第一材料的至少一部分 层和介电层的部分。

公开(公告)号：WO2011160011A1

公开(公告)日：2011-12-22

申请号：PCT/US2011/040874

申请日：2011-06-17

Applicant: SANDISK TECHNOLOGIES, INC. ,  PURAYATH, Vinod, Robert ,  MATAMIS, George ,  CHIEN, Henry ,  KAI, James ,  ZHANG, Yuan

Inventor： PURAYATH, Vinod, Robert ,  MATAMIS, George ,  CHIEN, Henry ,  KAI, James ,  ZHANG, Yuan

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/764

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

Abstract: High - density semiconductor memory is provided with enhancements to gate - coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric (438) between control gates (442) and charge storage regions (436) is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Dielectric caps (451,453) are provided between memory cells and have a dielectric constant smaller than the one of the intermediate dielectric (438). Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

Abstract translation: 高密度半导体存储器提供了对非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极（442）和电荷存储区域（436）之间的中间电介质（438）在行方向上变化，对于不同的材料，具有不同的介电常数以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 绝缘帽（451,453）设置在存储器单元之间并具有小于中间电介质（438）之一的介电常数。 至少部分地通过形成在列（位线）方向上的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

公开(公告)号：WO2014085108A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/070316

申请日：2013-11-15

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： PURAYATH, Vinod ,  KAI, James ,  ZHANG, Yuan ,  LEE, Donovan ,  MATAMIS, George

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

Abstract: Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches.

Abstract translation: 制造存储器件的方法包括在半导体衬底的存储器单元区域上形成隧道氧化物层，在存储单元区域中的隧道氧化物层上形成浮栅，浮栅层包含多个嵌入 电介质材料，在存储单元区域中的浮动栅极层上形成阻挡电介质层，去除存储单元区域中的阻挡介电层，浮栅，隧道氧化物层和半导体衬底的部分，以形成第一 多个隔离沟槽，以及在第一多个隔离沟槽内形成隔离材料。