公开(公告)号：WO2014189808A2

公开(公告)日：2014-11-27

申请号：PCT/US2014/038528

申请日：2014-05-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： PURAYATH, Vinod R. ,  KAI, James ,  LEE, Donovan ,  ZHANG, Yuan ,  MATSUDAIRA, Akira

IPC: H01L21/28

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/42324

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract translation: 一种非易失性存储器系统，包括具有在浮动栅极上具有倒T形的字线的非易失性存储装置。 倒T形形状具有较宽的底部部分和更薄的顶部部分。 较薄的顶部部分相对于较宽底部之间的间隔增加了相邻字线之间的间隔。 气隙可以分开相邻的字线。 字线的较薄顶部增加了相邻字线之间的路径长度。 可以通过减少相邻字线之间的电场来减小字线到字线短路的可能性。

公开(公告)号：WO2014163841A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/017955

申请日：2014-02-24

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： LEE, Donovan ,  KAI, James K. ,  SAMACHISA, George ,  CHIEN, Henry ,  MATAMIS, George ,  PURAYATH, Vinod R.

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/66825 ,  B82Y40/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887

Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Abstract translation: 一种存储器件和一种制造存储器件的方法，该器件包括半导体沟道，位于半导体沟道上方的隧道介电层，位于隧道介电层上方的浮动栅极，浮栅包括导电材料的连续层， 导电材料的至少一个突出物，面向隧道介电层并电连接到连续层，位于浮动栅极上方的阻挡电介质区域和位于阻挡电介质层上方的控制栅极。

公开(公告)号：WO2015112404A1

公开(公告)日：2015-07-30

申请号：PCT/US2015/011481

申请日：2015-01-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LEE, Donovan ,  PURAYATH, Vinod R. ,  KAI, James

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881

Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract translation: 悬浮电荷存储区域用于非易失性存储以减少寄生干扰并增加存储器件中的电荷保持。 电荷存储区域从覆盖的中间介电材料悬浮。 电荷存储区域包括在行和列方向上延伸的上表面和下表面。 电荷存储区域的上表面与上覆的中间介电材料耦合。 下表面面向基板表面，并通过空隙与基板表面分离。 电荷存储区包括在列方向上延伸的第一垂直侧壁和第二垂直侧壁以及沿行方向延伸的第三垂直侧壁和第四垂直侧壁。 第一，第二，第三和第四垂直侧壁通过空隙与非易失性存储器的相邻特征分离。 空隙可以包括真空，空气，气体或液体。

公开(公告)号：WO2015006152A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/045347

申请日：2014-07-03

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： CHIEN, Henry ,  LEE, Donovan ,  PURAYATH, Vinod R. ,  ZHANG, Yuan ,  KAI, James K. ,  MATAMIS, George

IPC: H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract translation: 一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括电绝缘材料，第二材料包括半导体或导体材料。 该方法还包括蚀刻堆叠以在堆叠中形成前侧开口，在暴露在前侧开口中的第一材料和第二材料的交替层的叠层上形成阻挡电介质层，形成半导体或金属电荷存储 在所述阻挡电介质上方形成在所述电荷存储层上方的隧道介电层，在所述隧道介电层上形成半导体沟道层，蚀刻所述堆叠以在所述堆叠中形成背侧开口，去除所述第一材料的至少一部分 层和介电层的部分。

公开(公告)号：WO2013012682A2

公开(公告)日：2013-01-24

申请号：PCT/US2012/046490

申请日：2012-07-12

Applicant: SANDISK TECHNOLOGIES INC. ,  PURAYATH, Vinod R. ,  KAI, James K. ,  PACHAMUTHU, Jayavel ,  LIANG, Jarrett Jun ,  MATAMIS, George ,  HONMA, Ryoichi

Inventor： PURAYATH, Vinod R. ,  KAI, James K. ,  PACHAMUTHU, Jayavel ,  LIANG, Jarrett Jun ,  MATAMIS, George ,  HONMA, Ryoichi

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract translation: 包括多个铜互连的半导体器件。 多个铜互连的至少第一部分在顶面中具有弯月面。 所述半导体器件还包括多个气隙，其中所述多个气隙中的每个气隙位于所述多个位线的至少所述第一部分的相邻对之间。