利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

217 条记录 (耗时 0.039 秒)

    VERTICAL INTERCONNECT METHODS FOR STACKED DEVICE ARCHITECTURES USING DIRECT SELF ASSEMBLY WITH HIGH OPERATIONAL PARALLELIZATION AND IMPROVED SCALABILITY
    2.
    发明申请
    VERTICAL INTERCONNECT METHODS FOR STACKED DEVICE ARCHITECTURES USING DIRECT SELF ASSEMBLY WITH HIGH OPERATIONAL PARALLELIZATION AND IMPROVED SCALABILITY 审中-公开
    采用直接自组装和高度可操作并行化和改进的可扩展性的堆叠设备架构的垂直互连方法

    公开(公告)号：WO2018063396A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/055012

    申请日：2016-09-30

    申请人： INTEL CORPORATION

    发明人： LILAK, Aaron D. ,  THEOFANIS, Patrick ,  MORROW, Patrick ,  MEHANDRU, Rishabh ,  CEA, Stephen M.

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

    摘要： An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.

    摘要翻译： 一种装置，包括由衬底上的电介质层分开的至少两个垂直堆叠的集成电路器件部件的阵列，其中所述至少两个垂直堆叠的层中的每一个包括横向布置的接触点 ; 以及导电互连，所述导电互连耦合到所述至少两个垂直堆叠层中的每一个的所述接触点的横向边缘并桥接所述介电层。 一种方法，包括：在衬底上形成由电介质层分开的至少两个垂直堆叠的集成电路器件部件层的阵列;形成暴露所述至少两个垂直堆叠层中的每一个的侧向接触点的沟槽; 在所述沟槽中沉积聚合物，其中所述聚合物优先对准所述横向接触点的材料并桥接所述电介质层; 并用导电材料改性或替换聚合物。

    THREE-DIMENSIONAL MEMORY DEVICE WITH CHARGE CARRIER INJECTION WELLS FOR VERTICAL CHANNELS AND METHOD OF MAKING AND USING THEREOF
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH CHARGE CARRIER INJECTION WELLS FOR VERTICAL CHANNELS AND METHOD OF MAKING AND USING THEREOF 审中-公开
    垂直通道带电荷载体注入井的三维记忆装置及其制造和使用方法

    公开(公告)号：WO2018038786A1

    公开(公告)日：2018-03-01

    申请号：PCT/US2017/035024

    申请日：2017-05-30

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： ZHANG, Yanli ,  ALSMEIER, Johann ,  KAI, James

    IPC分类号： H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11582

    CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/26513 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n- doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.

    摘要翻译： 掩埋源极半导体层和p掺杂半导体材料部分形成在衬底的第一部分之上。 掩埋源极半导体层是n-掺杂半导体材料，并且p-掺杂半导体材料部分嵌入掩埋源极半导体层内。 在衬底上形成交替的绝缘层和间隔材料层的叠层。 存储器堆栈结构通过交替堆栈形成。 间隔物材料层形成为导电层或被导电层取代。 掩埋源极半导体层可以在形成交替堆叠之前或之后形成。 掩埋源极半导体层位于交替堆叠之下并且覆盖衬底的第一部分，并接触垂直半导体沟道的至少一个表面。 p-掺杂半导体材料部分接触垂直半导体沟道的相应子集的至少一个表面。

    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A LATERAL SOURCE CONTACT AND METHOD OF MAKING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A LATERAL SOURCE CONTACT AND METHOD OF MAKING THE SAME 审中-公开
    含有横向接触点的三维记忆体装置及其制造方法

    公开(公告)号：WO2018031094A1

    公开(公告)日：2018-02-15

    申请号：PCT/US2017/034466

    申请日：2017-05-25

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： KANAKAMEDALA, Senaka ,  MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  SHARANGPANI, Rahul ,  KAI, James ,  LEE, Yao-Sheng

    IPC分类号： H01L27/1157 ,  H01L27/11582

    CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

    摘要： A sacrificial film and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. A memory stack structure including a memory film and a vertical semiconductor channel is formed through the alternating stack and the sacrificial film on the substrate. A source level cavity is formed by introducing an etchant or a reactant through a backside trench and removing the sacrificial film. After removal of an annular portion of the memory film, a portion of the vertical semiconductor channel is converted into an annular source region by introducing electrical dopants into the channel. A source contact layer is formed in the source level cavity and directly on the annular source region. The sacrificial material layers are replaced with electrically conductive layers. The annular source region and the source contact layer can provide low source contact resistance in a three-dimensional NAND memory device.

    摘要翻译： 在衬底上顺序形成牺牲膜和交替的绝缘层和牺牲材料层的叠层。 包括存储器膜和垂直半导体沟道的存储器堆叠结构穿过衬底上的交替堆叠和牺牲膜形成。 源级空腔通过经由背侧沟槽引入蚀刻剂或反应物并移除牺牲膜而形成。 在去除存储器膜的环形部分之后，通过将电掺杂剂引入到沟道中，将垂直半导体沟道的一部分转换成环形源极区。 源极接触层形成在源极水平腔中并且直接形成在环形源极区域上。 牺牲材料层被导电层替代。 环形源极区和源极接触层可以在三维NAND存储器件中提供低源极接触电阻。

    METHOD OF MAKING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE HAVING UNIFORM THICKNESS SEMICONDUCTOR CHANNEL
    5.
    发明申请
    METHOD OF MAKING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE HAVING UNIFORM THICKNESS SEMICONDUCTOR CHANNEL 审中-公开
    制造具有均匀厚度半导体沟道的三维半导体存储器件的方法

    公开(公告)号：WO2018004750A1

    公开(公告)日：2018-01-04

    申请号：PCT/US2017/019496

    申请日：2017-02-24

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： XU, Jiyin ,  HONMA, Ryoichi ,  FUKATA, Syo

    IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/1157

    CPC分类号： H01L27/1157 ,  H01L21/02063 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

    摘要翻译： 一种制造半导体器件的方法包括：在衬底上方形成包括绝缘层和间隔材料层的交替层的叠层;形成穿过所述叠层的存储开口;形成包括存储材料层 ，隧穿电介质层和第一半导体材料层，在第一半导体沟道层之上形成保护层，通过各向异性地蚀刻保护层和层堆叠的水平部分来物理地暴露层叠下方的半导体表面 在存储器开口的底部部分处，去除对第一半导体沟道层有选择性的保护层的剩余部分，并且在第一半导体沟道层上形成第二半导体沟道层。

    MEMORY DEVICES AND SYSTEMS HAVING REDUCED BIT LINE TO DRAIN SELECT GATE SHORTING AND ASSOCIATED METHODS
    8.
    发明申请
    MEMORY DEVICES AND SYSTEMS HAVING REDUCED BIT LINE TO DRAIN SELECT GATE SHORTING AND ASSOCIATED METHODS 审中-公开
    存储器件和系统具有减少的位线排出选择门闸及相关方法

    公开(公告)号：WO2017105737A1

    公开(公告)日：2017-06-22

    申请号：PCT/US2016/062273

    申请日：2016-11-16

    申请人： INTEL CORPORATION

    发明人： ZHU, Hongbin ,  ZHAO, Jun ,  NARAYANAN, Purnima ,  HALLER, Gordon ,  FAZIL, Damir

    IPC分类号： H01L27/1157 ,  H01L27/11582

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

    摘要： A method of forming a memory structure (figures 3i - 3j), comprising: providing a layered semiconductor substrate (304) having a contact region (302), a source select gate (306, SGS) layer on the contact region, and a tiered stack of semiconductor layers (308) on the SGS layer; forming a drain select gate (312, SGD) layer on the tiered stack of the semiconductor substrate; forming a nitride isolation layer (314) on the SGD layer; forming an oxide isolation layer (316) on the nitride isolation layer; etching a pillar trench from the oxide isolation layer into the contact region of the semiconductor substrate; forming a central pillar (318, 320, 322) in the pillar trench from the contact region at least into the nitride isolation layer; forming a plug recess (328, 330) by etching sidewalls of the oxide isolation around the pillar trench to expose a portion of a top surface of the nitride isolation layer; forming a T-plug (332) in the plug recess; and forming an electrical contact (336) on the T-plug such that the T-plug (332) provides a barrier against electrical shorting from the electrical contact (336) to the SGD layer (312).

    摘要翻译： 一种形成存储器结构的方法（图3i-3j），包括：提供具有接触区域（302），源极选择栅极（306，SGS）层的分层半导体衬底（304） 在所述接触区域上，以及在所述SGS层上的层叠的半导体层（308）堆叠; 在所述半导体衬底的所述分层堆叠上形成漏​​极选择栅极（312，SGD）层; 在SGD层上形成氮化物隔离层（314）; 在所述氮化物隔离层上形成氧化物隔离层（316） 蚀刻从所述氧化物隔离层到所述半导体衬底的接触区域的柱沟槽; 在所述柱沟槽中从所述接触区形成中心柱（318,320,322）至少进入所述氮化物隔离层; 通过蚀刻围绕柱状沟槽的氧化物隔离的侧壁来形成插塞凹槽（328,330）以暴露氮化物隔离层的顶表面的一部分; 在插塞凹槽中形成T形插塞（332） 以及在T形插头上形成电触头（336），使得T形插头（332）提供防止从电触头（336）到SGD层（312）的电短路的屏障。

    THREE-DIMENSIONAL NAND DEVICE CONTAINING SUPPORT PEDESTAL STRUCTURES FOR A BURIED SOURCE LINE AND METHOD OF MAKING THE SAME
    10.
    发明申请
    THREE-DIMENSIONAL NAND DEVICE CONTAINING SUPPORT PEDESTAL STRUCTURES FOR A BURIED SOURCE LINE AND METHOD OF MAKING THE SAME 审中-公开
    用于埋入源管线的包含支撑顶部结构的三维NAND器件及其制造方法

    公开(公告)号：WO2017087048A1

    公开(公告)日：2017-05-26

    申请号：PCT/US2016/049986

    申请日：2016-09-01

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： KAI, James ,  ALSMEIER, Johann ,  LIU, Jin ,  ZHANG, Yanli

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344

    摘要： A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

    摘要翻译： 三维存储器件包括位于衬底之上的导电层和绝缘层的交替堆叠，存储器堆叠结构的阵列。 在基板和交替叠层之间提供交替顺序的支撑基座结构和沿相同水平方向延伸的导电轨道结构。 每个存储器堆叠结构横跨导电轨道结构和支撑基座结构之间的垂直界面。 每个存储器堆叠结构中的半导体沟道接触相应的导电轨道结构，并且通过存储器膜的一部分与相邻的支撑基座结构电隔离。 导电轨道结构可以用作存储设备的源区。