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    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END FULLY SELF-ALIGNED INTERCONNECT PROCESS
    2.
    发明申请
    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END FULLY SELF-ALIGNED INTERCONNECT PROCESS 审中-公开

    公开(公告)号：WO2019183035A1

    公开(公告)日：2019-09-26

    申请号：PCT/US2019/022882

    申请日：2019-03-19

    Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    Inventor： CLARK, Robert ,  TAPILY, Kandabara ,  YU, Kai-Hung

    IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285

    Abstract: Method for forming a fully self-aligned via is provided. Workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

    SELECTIVE DEPOSITION OF CONDUCTIVE CAP FOR FULLY-ALIGNED-VIA (FAV)
    4.
    发明申请
    SELECTIVE DEPOSITION OF CONDUCTIVE CAP FOR FULLY-ALIGNED-VIA (FAV) 审中-公开

    公开(公告)号：WO2021158748A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/016556

    申请日：2021-02-04

    Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    Inventor： LU, Yen-Tien ,  YU, Kai-Hung ,  SUN, Xinghua ,  RALEY, Angelique

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/67

    Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

    SACRIFICIAL GATE CAPPING LAYER FOR GATE PROTECTION
    7.
    发明申请
    SACRIFICIAL GATE CAPPING LAYER FOR GATE PROTECTION 审中-公开

    公开(公告)号：WO2022240677A1

    公开(公告)日：2022-11-17

    申请号：PCT/US2022/028050

    申请日：2022-05-06

    Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    Inventor： HAN, Yun ,  LIU, Eric Chih-Fang ,  YU, Kai-Hung ,  CHANG, Shihsheng ,  RANJAN, Alok

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

    RUTHENIUM METAL DEPOSITION METHOD FOR ELECTRICAL CONNECTIONS
    10.
    发明申请
    RUTHENIUM METAL DEPOSITION METHOD FOR ELECTRICAL CONNECTIONS 审中-公开
    用于电连接的钌金属沉积方法

    公开(公告)号：WO2017143180A1

    公开(公告)日：2017-08-24

    申请号：PCT/US2017/018356

    申请日：2017-02-17

    Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

    Inventor： YU, Kai-Hung ,  LEUSINK, Gerrit J. ,  WAJDA, Cory ,  ISHIZAKA, Tadahiro ,  HAKAMATA, Takahiro

    IPC: C23C16/18 ,  C23C16/04 ,  C23C16/44 ,  C23C16/448 ,  H01L21/285

    CPC classification number: C23C16/16 ,  C23C16/4408 ,  C23C16/4481 ,  C23C16/45523 ,  C23C16/45557

    Abstract: A method for material deposition is described in several embodiments. According to one embodiment, the method includes providing a substrate defining features to receive a deposition of material, initiating a flow of a Ru carbonyl precursor to the substrate, the Ru carbonyl precursor decomposing within the defined features such that a Ru metal film is deposited on surfaces of the defined features and CO gas is released, and stopping the flow of the Ru carbonyl precursor to the substrate. The method further includes flowing additional CO gas to the substrate after stopping the flow of the Ru carbonyl precursor to the substrate, and repeatedly cycling between process steps of flowing the Ru carbonyl precursor to the substrate and flowing the additional CO gas to the substrate. In one embodiment, the Ru carbonyl precursor contains Ru 3 (CO) 12 .

    Abstract translation: 在几个实施例中描述了用于材料沉积的方法。 根据一个实施例，该方法包括提供限定特征的衬底，以接收材料的沉积，开始羰基Ru前体向衬底的流动，Ru羰基前体在限定的特征内分解，使得Ru金属膜沉积在 限定特征的表面和CO气体被释放，并且停止羰基Ru前体向基底的流动。 该方法进一步包括在停止羰基Ru前体向基材的流动之后，将额外的CO气体流入基材，并且在使羰基Ru前体流至基材并使另外的CO气体流至基材的工艺步骤之间重复循环。 在一个实施方案中，Ru羰基前体含有Ru 3（CO）12。

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