公开(公告)号：WO2015120217A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014730

申请日：2015-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: H04L25/49 ,  H04L12/40

CPC classification number: H03M5/20 ,  G06F13/4221 ,  H03M5/16 ,  H04L12/40182 ,  H04L25/4917 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data bus (206) is split into partitions (218, 216) and encoding (214, 212) is independently applied to data transmitted over each bus partition to improve power and/or throughput efficiency. The encoding can be data bus inversion or any other suitable type of encoding. An encoding indicator symbol (226) transmitted in conjunction with the data indicates which bus partition is encoded, if any. In some implementations, encoding is selectively applied to each bus partition during each data transfer cycle of a parallel data bus. In some implementation, the encoding indicator symbol is a multi-level signal where each level of the multi-level signal represents at least two bits of information indicative of, for a corresponding bus partition, whether encoding is applied to the data to be transmitted over the bus partition. Advantageously, the encoding indicator symbol can be transmitted over a single, dedicated bus line.

Abstract translation: 数据总线（206）被分割成分区（218,216），并且编码（214,212）被独立地应用于通过每个总线分区传输的数据，以提高功率和/或吞吐量效率。 编码可以是数据总线反转或任何其他合适类型的编码。 与数据一起发送的编码指示符符号（226）指示哪个总线分区被编码（如果有的话）。 在一些实现中，在并行数据总线的每个数据传输周期期间，编码被选择性地应用于每个总线分区。 在一些实现中，编码指示符符号是多级信号，其中多级信号的每个级别表示至少两比特的信息，指示对于相应的总线分区，是否将编码应用于要发送的数据 总线分区。 有利地，编码指示符符号可以通过单个专用总线发送。

公开(公告)号：WO2015157627A1

公开(公告)日：2015-10-15

申请号：PCT/US2015/025301

申请日：2015-04-10

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: H04L25/49

CPC classification number: G06F13/4018 ,  G06F13/4022 ,  G06F13/42 ,  H04L25/4917

Abstract: Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed.

Abstract translation: 公开了通过叠加进行总线频率控制的系统和方法。 在一个实施例中，代替添加引脚或增加总线的工作频率，使用叠加将三个信号放置在总线内的线上。 以这种方式，可以通过两个导体发送三个比特，从而有效地避免了对附加引脚的需要，并且有效地增加了比特传输的频率，而不必增加时钟速度。

公开(公告)号：WO2015191238A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/031147

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry ,  BRUNOLLI, Michael Joseph

IPC: G11C7/10 ,  G06F13/42 ,  H04L25/02 ,  G11C5/06 ,  H03K19/0185 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/02

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G06F13/4243 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  H03K19/018521 ,  H03K19/018528 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract translation: 提供源同步系统，其中在数据源端点以及数据宿端点中可能存在非均匀接口。

公开(公告)号：WO2015103290A2

公开(公告)日：2015-07-09

申请号：PCT/US2014/072798

申请日：2014-12-30

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: G11C29/02

CPC classification number: G11C29/36 ,  G06F11/263 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1206 ,  G11C2029/3602

Abstract: One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.

Abstract translation: 一个特征是从多个模式寄存器读取数据的方法，从读取的数据在映射寄存器处生成第一输出，在映射寄存器处产生与第一输出不同的第二输出与读取的数据，并产生 使用第一和第二输出的多电平信号。 在一个实施例中，通过将第一多个比特添加到第二多个比特来生成第一输出，并且通过将第一多个比特相加到第二多个比特的倒数来生成第二输出。

公开(公告)号：WO2015077066A1

公开(公告)日：2015-05-28

申请号：PCT/US2014/064760

申请日：2014-11-10

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: H03K19/00 ,  G06F13/38 ,  H03K19/0175

CPC classification number: H04L1/0042 ,  G06F13/38 ,  H03K19/0008 ,  H03K19/0175 ,  H04L1/0075

Abstract: Electronic devices are adapted to facilitate data encoding for simultaneously limiting both instantaneous current and signal transitions. According to one example, an electronic device may perform a first encoding scheme on a group of data bits to be transmitted on a data bus. The first encoding scheme may be performed based on a number of transitions within the group of data bits for each data channel. A second encoding scheme may also be performed on the group of data bits. The second encoding scheme may be performed based on a number of data bits within the group of data bits for each data channel exhibiting a predetermined state (e.g., a one or a zero). After both encoding scheme are performed on the group of data bits, the encoded data bits may be transmitted over respective data channels of the data bus. Other aspects, embodiments, and features are also included.

Abstract translation: 电子设备适于促进数据编码，以同时限制瞬时电流和信号转换。 根据一个示例，电子设备可以在要在数据总线上发送的一组数据位上执行第一编码方案。 第一编码方案可以基于每个数据信道的数据比特组内的多个转换来执行。 还可以对该组数据位执行第二编码方案。 可以基于表示预定状态（例如，一个或零）的每个数据信道的数据比特组内的数据比特数来执行第二编码方案。 在对数据位组执行两个编码方案之后，编码数据位可以在数据总线的相应数据通道上发送。 还包括其他方面，实施例和特征。

公开(公告)号：WO2015103289A1

公开(公告)日：2015-07-09

申请号：PCT/US2014/072795

申请日：2014-12-30

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: G11C29/02 ,  G11C29/36

CPC classification number: G11C29/36 ,  G11C29/022 ,  G11C2029/1206 ,  G11C2029/3602

Abstract: One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of data patterns is derived from the single data pattern, and the plurality of data patterns may be used in a test and sent to an output driver of the memory circuit. The plurality of data patterns may include a first data pattern and a second data pattern. The first data pattern may be derived from the single data pattern. The second data pattern is one of either a true copy of the single data pattern, an inverse copy of the single data pattern, an all zero bits data pattern, or an all one bits data pattern.

Abstract translation: 一个特征涉及从位于存储器电路或设备内的模式寄存器读取的单个数据模式。 从单个数据模式导出多个数据模式中的至少一个，并且可以在测试中使用多个数据模式并将其发送到存储器电路的输出驱动器。 多个数据模式可以包括第一数据模式和第二数据模式。 第一数据模式可以从单个数据模式导出。 第二数据模式是单个数据模式的真实副本，单个数据模式的逆副本，全零位数据模式或全1位数据模式之一。

公开(公告)号：WO2015077606A1

公开(公告)日：2015-05-28

申请号：PCT/US2014/066891

申请日：2014-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: H04L25/49 ,  G06F13/38 ,  H03M5/02

CPC classification number: H04L25/4917 ,  G06F13/38 ,  H03M5/02 ,  H04L25/4915

Abstract: System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.

Abstract translation: 描述了减少由多级编码通信链路消耗的功率的系统，方法和装置。 在一个示例中，4级脉冲幅度调制编码传输的不同逻辑状态消耗比其他逻辑状态更大的功率。 多比特数据符号中的第一逻辑状态中的主比特的分数可以确定在传输之前主比特是否被反转。 在多位数据符号中的第一逻辑状态中的副位的分数可以确定辅助位在传输之前是否被反转。 主位可以被交换，次级位比第一逻辑状态中的主位更多次次位处于第一逻辑状态。

公开(公告)号：WO2014150529A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/023508

申请日：2014-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry

IPC: G06F13/42

CPC classification number: G06F13/4286 ,  G06F13/287 ,  G06F13/4221 ,  G06F13/4226 ,  H04L7/04 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

Abstract translation: 描述用于数据传输的方法。 确定电子设备的信号传输速度。 基于信令操作速度选择数据总线反演算法。 所选择的数据总线反演算法用于对数据进行编码。 编码数据和数据总线反转标志通过传输介质发送到接收器。

公开(公告)号：WO2016053463A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/043305

申请日：2015-07-31

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry ,  BRYAN, Thomas Clark ,  WAYLAND, Mark

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K3/011 ,  G11C11/4096 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018585

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract translation: 公开了基于来自校准驱动电路的输出阻抗的信息来均衡输出驱动器电路的系统和方法。 由校准产生的设置称为校准代码。 输出驱动器电路包括多个上拉元件，其在输出为高电平时使能或禁止产生期望的输出阻抗，并且当输出为低电平时启用或禁用以产生所需输出阻抗的多个下拉元件。 启用的上拉元件数量和启用的下拉元件数量通过校准设置。 校准的结果（即，上拉的使能元件数量和下拉使能元件的数量）用于设置预加重量的控制和/或设置输出转换的控制 率。

公开(公告)号：WO2016007221A1

公开(公告)日：2016-01-14

申请号：PCT/US2015/030992

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan Jee ,  HOLLIS, Timothy Mowry

IPC: H04L25/02

CPC classification number: H04L25/4927 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/06 ,  H04L25/4915 ,  H04L25/4917 ,  H04L27/06

Abstract: High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the "floor voltage" that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.

Abstract translation: 处理器和片外DRAM之间的高速数据链路利用脉冲幅度调制（PAM）信号来提高SoC中给定带宽和资源预算的数据速率。 然而，处理器和DRAM之间的传输线接口中使用的终端电阻在PAM信令期间消耗大量的功率。 通过在接地端子和终端电阻之间增加一个偏压源，终端电阻器用作确定信号电平的基准的“底电压”可能会提高。 提高地板电压会降低终端电阻两端的电压，从而降低功耗。 偏置源被调整到PAM信号的最大幅度的各种增量。 PAM信令的最大幅度的一半的地板电压在接收机中产生最小功耗。 另外，数据反转预编码可以与底层电压调整相连接，以进一步最大化接口的功率节省。