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    LONG WAVELENGTH VCSEL COMPRISING A TUNNEL JUNCTION WITH CARBON DOPED GAASSB
    1.
    发明申请
    LONG WAVELENGTH VCSEL COMPRISING A TUNNEL JUNCTION WITH CARBON DOPED GAASSB 审中-公开
    长波长VCSEL包括带有碳酸钙的隧道接头

    公开(公告)号：WO03073565A2

    公开(公告)日：2003-09-04

    申请号：PCT/US0305471

    申请日：2003-02-21

    Applicant: HONEYWELL INT INC

    Inventor： KWON HO-KI

    IPC: H01L21/20 ,  H01L21/205 ,  H01L21/329 ,  H01L29/88 ,  H01S5/183 ,  H01S5/32 ,  H01S3/00

    CPC classification number: H01S5/18308 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66151 ,  H01L29/88 ,  H01S5/18358 ,  H01S5/3054 ,  H01S5/3095 ,  H01S5/3215 ,  H01S2301/173 ,  H01S2304/04

    Abstract: GaAs(1-x)Sbx layers are grown by MOCVD. For lattice matching with InP, x is set to 0.5, while beneficial alternatives include setting x to 0.23, 0.3, and 0.4. During MOVCD, TMGa (or TEGa), TMSb, and AsH3 (or TBAs) are used to fabricate the GaAs(1-x)Sbx layer. Beneficially, the GaAs(1-x)Sbx layer's composition is controlled by the ratio of As to Sb. The MOCVD growth temperature is between 500 °C and 650 °C. The GaAs(1-x)Sbx layer is beneficially doped using CCl4 or CBr4. A heavily doped GaAs(1-x)Sbx layer can be used to form a tunnel junction with n-doped layers of InP, AlInAs, or with lower bandgap materials such as AlInGaAs or InGaAsP. Such tunnel junctions are useful for producing long wavelength VCSELs.

    Abstract translation: 通过MOCVD生长GaAs（1-x）Sbx层。 对于与InP的晶格匹配，x被设置为0.5，而有益的替代方案包括将x设置为0.23,0.3和0.4。 在MOVCD期间，使用TMGa（或TEGa），TMSb和AsH3（或TBAs）来制造GaAs（1-x）Sbx层。 有利地，GaAs（1-x）Sbx层的组成由As与Sb的比例控制。 MOCVD生长温度在500°C和650°C之间。 GaAs（1-x）Sbx层有利地用CCl4或CBr4掺杂。 可以使用重掺杂的GaAs（1-x）Sbx层来形成具有In掺杂的InP，AlInAs或者较低带隙材料如AlInGaAs或InGaAsP的隧道结。 这种隧道结可用于生产长波长VCSEL。

    COMPACT MEMORY STRUCTURE INCLUDING TUNNELING DIODE
    4.
    发明申请
    COMPACT MEMORY STRUCTURE INCLUDING TUNNELING DIODE 审中-公开
    包含隧道二极管的紧凑型存储器结构

    公开(公告)号：WO2015138731A1

    公开(公告)日：2015-09-17

    申请号：PCT/US2015/020193

    申请日：2015-03-12

    Applicant: QUTEL, INC. ,  BERGER, Paul

    Inventor： BERGER, Paul

    IPC: H01L29/88

    CPC classification number: H01L29/882 ,  G11C11/40603 ,  G11C11/417 ,  H01L27/1052 ,  H01L27/10805 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/365 ,  H01L29/66121 ,  H01L29/66151

    Abstract: A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a "hybrid" memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency.

    Abstract translation: 可以使用类似于用于互补金属氧化物半导体（CMOS）器件制造的半导体处理来制造谐振带间隧道二极管（RITD），例如可以包括使用硅。 可以制造存储单元（例如，随机存取存储器（RAM）单元）以包括一个或多个负差分电阻器件，例如隧道二极管，以提供单位或多位单元。 在一个示例中，可以制造“混合”存储单元，例如包括一个或多个负电阻器件，MOS晶体管结构和电容器结构，例如包括类似于通常可用的动态RAM的集成电容器配置（ DRAM）结构，但不需要刷新并提供更高的面积效率。

    METHOD OF MANUFACTURE FOR 80 NANOMETER DIAMETER RESONANT TUNNELING DIODE WITH IMPROVED PEAK-TO-VALLEY RATIO AND RESONANT TUNNELING DIODE THEREFROM
    5.
    发明申请
    METHOD OF MANUFACTURE FOR 80 NANOMETER DIAMETER RESONANT TUNNELING DIODE WITH IMPROVED PEAK-TO-VALLEY RATIO AND RESONANT TUNNELING DIODE THEREFROM 审中-公开
    80纳米直径共振隧道二极管的制造方法与改进的峰谷比和谐振隧道二极管

    公开(公告)号：WO2003015283A2

    公开(公告)日：2003-02-20

    申请号：PCT/US2002/025241

    申请日：2002-08-07

    Applicant: HRL LABORATORIES, LLC ,  THOMAS, Stephen ,  CHOW, David ,  ELLIOTT, Ken

    Inventor： THOMAS, Stephen ,  CHOW, David ,  ELLIOTT, Ken

    IPC: H03M

    CPC classification number: B82Y10/00 ,  H01L29/66151 ,  H01L29/882 ,  Y10S977/712 ,  Y10S977/888

    Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyamide passivation and planerization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate (706) that serves as a foundation for bottom contact layer (708) and a polyamide (700) coating. An ohmic metal contact (702) and emitter metal contact (704) protrude above the polyamide (700) coating exposing the ohmic metal contact (702) and emitter metal contact (704). The contacts are capped with an etch resistant coating (710) thus allowing for the polyamide etch, and other etching processes without adversely affecting the contacts.

    Abstract translation: 约80纳米直径的亚微米，具有约5.1比1的峰谷比的共振隧道二极管及其制造方法。 本发明是独特的，因为其性能特性在相当大的谐振隧道二极管中是无法比拟的。 此外，聚酰胺钝化和平面化方法提供了在制造谐振隧道二极管中的应用方面的意想不到的处理优点。 本发明包括用作底部接触层（708）和聚酰胺（700）涂层的基础的基底（706）。 欧姆金属触点（702）和发射极金属触点（704）突出在暴露欧姆金属触点（702）和发射极金属触点（704）的聚酰胺（700）涂层之上。 触点用耐蚀刻涂层（710）封盖，从而允许聚酰胺蚀刻和其它蚀刻工艺，而不会不利地影响触点。

    METAL-INSULATOR-METAL DIODES AND METHODS OF FABRICATION
    7.
    发明申请
    METAL-INSULATOR-METAL DIODES AND METHODS OF FABRICATION 审中-公开
    金属绝缘体 - 金属二极管和制造方法

    公开(公告)号：WO2015016861A2

    公开(公告)日：2015-02-05

    申请号：PCT/US2013052868

    申请日：2013-07-31

    Applicant: EMPIRE TECHNOLOGY DEV LLC

    Inventor： SEIKE AYA

    IPC: H01L29/861

    CPC classification number: H01L29/66151 ,  C23C14/24 ,  C23C14/54 ,  G03F7/162 ,  G03F7/20 ,  G03F7/32 ,  H01L21/67069 ,  H01L29/861 ,  H01L45/00

    Abstract: Provided herein are embodiments relating to metal-insulator-metal diodes and their method of manufacture. In some embodiments, the metal-insulator-metal diodes can be made, in part, via the use of an evanescent wave on a photo resist. In some embodiments, this allows for finer manipulation of the photo resist and allows for the separation of one piece of metal into a first and second piece of metal. The first piece of metal can then be differentially treated from the second (for example, by annealing another metal to the first piece), to allow for a difference in the work function of the two pieces of metal.

    Abstract translation: 本文提供了涉及金属 - 绝缘体 - 金属二极管及其制造方法的实施例。 在一些实施例中，金属 - 绝缘体 - 金属二极管可以部分地通过在抗蚀剂上使用ev逝波来制造。 在一些实施例中，这允许对光致抗蚀剂进行更精细的操作并且允许将一片金属分离成第一和第二金属片。 然后可以将第一块金属与第二块金属（例如，通过将另一种金属退火到第一块）进行差异化处理，以允许两块金属的功函数不同。

    DIODES, AND METHODS OF FORMING DIODES
    8.
    发明申请
    DIODES, AND METHODS OF FORMING DIODES 审中-公开
    二极体和形成二极体的方法

    公开(公告)号：WO2009154935A2

    公开(公告)日：2009-12-23

    申请号：PCT/US2009044801

    申请日：2009-05-21

    Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S ,  MOULI CHANDRA

    Inventor： SANDHU GURTEJ S ,  MOULI CHANDRA

    IPC: H01L29/861

    CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

    Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

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