公开(公告)号：WO2008119179A1

公开(公告)日：2008-10-09

申请号：PCT/CA2008/000609

申请日：2008-04-03

Applicant: SCANIMETRICS INC. ,  SLUPSKY, Steven ,  MOORE, Brian ,  SELLATHAMBY, Christopher V.

Inventor： SLUPSKY, Steven ,  MOORE, Brian ,  SELLATHAMBY, Christopher V.

IPC: G01R1/067 ,  G01R1/07 ,  G01R1/30 ,  G01R31/3185

CPC classification number: G01R1/06711 ,  G01R1/06722 ,  G01R1/06727 ,  G01R1/07307 ,  G01R1/07342 ,  G01R1/07385 ,  G01R31/3025 ,  G01R31/318505 ,  G01R31/31905

Abstract: A method and apparatus are provided for transmission/reception of signals between automatic test equipment (ATE) and a device under test (DUT). A probe card has a plurality of associated proximate active probe integrated circuits (APIC) connected to a plurality of probes. Each APIC interfaces with one or more test interface points on the DUT through probes. Each APIC receives and processes signals communicated between the ATE and the DUT. Low information content signals transmitted from the ATE are processed into high information content signals for transmission to the probe immediately adjacent the APIC, and high information content or time critical signals received by the APIC from the DUT are transmitted as low information content signals to the ATE. Because the APIC is immediately adjacent the probe there is minimum loss or distortion of the information in the signal from the DUT.

Abstract translation: 提供了用于在自动测试设备（ATE）和被测设备（DUT）之间发送/接收信号的方法和设备。 探针卡具有连接到多个探针的多个相关的近端有源探针集成电路（APIC）。 每个APIC通过探头与DUT上的一个或多个测试接口点连接。 每个APIC都接收并处理ATE和DUT之间传送的信号。 从ATE传输的低信息内容信号被处理成高信息内容信号以传输到紧邻APIC的探测器，并且由APIC从DUT接收的高信息内容或时间关键信号作为低信息内容信号被传输到ATE 。 由于APIC紧邻探头，因此DUT信号中的信息损失最小。

公开(公告)号：WO2007024656A2

公开(公告)日：2007-03-01

申请号：PCT/US2006/032268

申请日：2006-08-18

Applicant: INAPAC TECHNOLOGY, INC. ,  ONG, Adrian E.

Inventor： ONG, Adrian E.

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/31926 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G01R31/31917

Abstract: In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.

Abstract translation: 在一个实施例中，本发明提供了一种硬件和/或软件的平台，其使得能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。 该平台可以包括测试组件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶圆探测器程序，外部测试设备的负载板和相关硬件以及软件和例程 为最终的测试程序。

公开(公告)号：WO2006115779A1

公开(公告)日：2006-11-02

申请号：PCT/US2006/013607

申请日：2006-04-10

Applicant: RAMBUS INC. ,  ECHEVARRIA, Victor

Inventor： ECHEVARRIA, Victor

IPC: G01R31/3185

CPC classification number: G01R31/318505

Abstract: A technique for testing interconnections between electronic components is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for testing interconnections between electronic components. The method may comprise sending a command from a test controller to a plurality of electronic components via a first communication path, wherein the command comprises an instruction for one or more of the plurality of electronic components to transmit a recognizable data pattern to the test controller via a second communication path. The method may also comprise isolating a failure in the first communication path based upon the recognizable data pattern not being transmitted to the test controller via the second communication path.

Abstract translation: 公开了一种用于测试电子部件之间的互连的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于测试电子部件之间的互连的方法。 该方法可以包括经由第一通信路径将测试控制器的命令从测试控制器发送到多个电子部件，其中该命令包括用于多个电子部件中的一个或多个的指令，以将可识别的数据模式发送到测试控制器，该测试控制器经由 第二通信路径。 该方法还可以包括基于经由第二通信路径不被发送到测试控制器的可识别数据模式来隔离第一通信路径中的故障。

公开(公告)号：WO2003067271A2

公开(公告)日：2003-08-14

申请号：PCT/US2003/002852

申请日：2003-01-31

Applicant: OPTONICS, INC. ,  PAKDAMAN, Nader ,  KASAPI, Steven ,  GOLDBERGER, Itzik

Inventor： PAKDAMAN, Nader ,  KASAPI, Steven ,  GOLDBERGER, Itzik

IPC: G01R31/00

CPC classification number: G01R31/318505 ,  G01R31/311 ,  G01R31/318511

Abstract: Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser. The electrical activity within the circuit in response to the test signal is sensed by a receiver element, such as a time-resolved photon counting detector, a static emission camera system, or by an active laser probing system. The collected information is used for a variety of purposes, including manufacturing process monitoring, new process qualification, and model verification.

Abstract translation: 与本发明的原理一致的系统和方法允许在集成电路内的各种电活动的非接触式测量。 本发明可以用于在器件处理的各个阶段期间的晶片上的各种器件的高带宽，速度测试，或者在制造周期结束时的封装部件上。 使用传统的机械探针或其他手段（例如施加到设置在测试电路上的光接收器的CW激光）将功率施加到测试电路。 电测试信号通过使用非接触方法来刺激电路而被引入到测试电路中，例如通过将一个或多个锁模激光器的输出引导到电路上的高速接收器上，或者通过使用高速脉冲二极管激光器 。 响应于测试信号的电路内的电活动由诸如时间分辨光子计数检测器，静态发射照相机系统或主动激光探测系统的接收器元件感测。 收集的信息用于各种目的，包括制造过程监控，新工艺认证和型号验证。

公开(公告)号：WO03030214A2

公开(公告)日：2003-04-10

申请号：PCT/IB0203824

申请日：2002-09-17

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： VAN ARENDONK ANTON P M ,  ROKS EDWIN ,  MIEROP ADRIANUS J

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3187 ,  H01L21/66 ,  H01L21/822 ,  H01L23/58 ,  H01L27/04 ,  H01L

CPC classification number: G01R31/318505 ,  G01R31/318511 ,  G01R31/3187

Abstract: The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the manufacturing method, and a system comprising an integrated circuit (404) obtained by means of the manufacturing method.

Abstract translation: 本发明涉及在芯片（402）上制造集成电路（404）的方法，其中模具（402）形成晶片（401）的可拆卸部分，该晶片包括通过切割相互分离的多个管芯 车道（403）。 该方法包括在至少一个切割通道（403）中施加金属化图案（407）以形成包括作为集成电路（404）的一部分的至少一个通信总线电路（405）的通信总线的步骤。 所述步骤之后是其中根据使用通信总线电路（405）与集成电路（404）通信的预定测试方法测试集成电路（404）的步骤。 该步骤之后是其中模具（402）与晶片（401）分离的下一步骤。 通信总线电路（405）被设计成在晶片测试模式以及功能模式下进行通信。 在集成电路（404）的测试期间，它以晶片测试模式进行通信。 本发明还涉及通过制造方法获得的集成电路（404），包括通过制造方法获得的集成电路（404）的晶片（401），以及包括获得的集成电路（404）的系统， 通过制造方法。

公开(公告)号：WO2002075337A2

公开(公告)日：2002-09-26

申请号：PCT/US2002/008627

申请日：2002-03-19

Applicant: SCHLUMBERGER TECHNOLOGIES, INC. ,  DALLA RICCA, Paolo ,  WEST, Burnell, G.

Inventor： DALLA RICCA, Paolo ,  WEST, Burnell, G.

IPC: G01R31/00

CPC classification number: G01R31/31709 ,  G01R31/318505 ,  G01R31/31917 ,  G01R31/31922 ,  G01R31/31937 ,  G11C29/10 ,  G11C29/56 ,  G11C2029/0401

Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.

Abstract translation: 为被测设备（DUT）生成测试信号涉及产生主参考信号，使用游标技术根据主参考信号生成测试模式信号，产生与第一参考信号相位匹配的测试时钟信号，并与 通过将主参考信号作为输入提供给锁相环（PLL）并控制PLL中的一个或多个可编程分频器以将测试时钟信号调整为测试频率的倍数或次倍，来测试模式信号 将测试时钟信号施加到DUT的时钟输入引脚，并将测试模式信号施加到DUT的数据引脚。 当测试图形信号的频率改变时，可以通过重新编程可编程分频器来调整测试时钟信号频率以校准测试图形信号的变化频率。

公开(公告)号：WO01016611A1

公开(公告)日：2001-03-08

申请号：PCT/US2000/023858

申请日：2000-08-30

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/267 ,  G06F13/00 ,  G06F13/362

CPC classification number: G01R31/318505 ,  G06F11/221

Abstract: A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. Abus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block. Alternatively, a centralized test device controller is used to disable the output of the second functional block, as opposed to using the grant signals of the bus arbiter. This allows the incorporation of the implementing logic without altering the logic of the bus arbiter.

Abstract translation: 一种用于在测试期间防止多功能集成电路中的总线竞争的系统。 该系统在集成电路中实现，该集成电路适于接受用于测试集成电路功能的一系列测试输入。 集成电路包括用于通信地耦合多个功能块的至少一个总线。 至少包括在集成电路中的第一功能块和第二功能块，第一功能块和第二功能块都耦合到总线并被耦合以接受测试输入。 Abus仲裁员也被包括在授予公共汽车所有权的集成电路中。 如果通过使用为第一功能块生成的总线许可信号来激活第一功能块的相应输出，则总线仲裁器可操作以禁用第二功能块的至少一个输出。 这确保测试输入可以通过第一功能块和第二功能块传播，而不会导致第一功能块和第二功能块之间的总线的争用。 或者，与使用总线仲裁器的授权信号相反，集中测试设备控制器用于禁用第二功能块的输出。 这允许并入执行逻辑，而不改变总线仲裁器的逻辑。

公开(公告)号：WO01016610A1

公开(公告)日：2001-03-08

申请号：PCT/US2000/023650

申请日：2000-08-29

IPC: G06F13/362 ,  G01R31/3185 ,  G06F11/267 ,  G06F13/00

CPC classification number: G01R31/318505 ,  G06F11/221

Abstract: A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit (100) adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus (110) for communicatively coupling the multiple functional blocks (101-104). At least a first functional block and a second functional block are included in the integrated circuit, the first functional block and the second functional block both being coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus (110) between the first functional block and the second functional block.

Abstract translation: 一种用于在被测试的多功能集成电路中防止总线竞争的系统。 该系统在适于接受可操作用于测试集成电路的功能的一系列测试输入的集成电路（100）中实现。 集成电路包括用于通信地耦合多个功能块（101-104）的至少一个总线（110）。 至少第一功能块和第二功能块包括在集成电路中，第一功能块和第二功能块都耦合到总线并被耦合以接受测试输入。 集成电路中还包括一个输出使能控制器。 输出使能控制器耦合到第二功能块，并且如果第一功能块的相应输出被激活，则可操作地禁用第二功能块的至少一个输出。 这确保测试输入可以通过第一功能块和第二功能块传播，而不会导致第一功能块和第二功能块之间的总线（110）的争用。

公开(公告)号：WO99066337A2

公开(公告)日：1999-12-23

申请号：PCT/DE1999/001719

申请日：1999-06-11

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/31708 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318572 ,  G01R31/31926

Abstract: According to the invention, one or more external test connection contact points (pads; pins; balls), (2, 3) are provided in an integrated circuit component (chip) (1), through which signals (4, 5, 6) that are to be measured or analyzed are selectively fed, e.g. by means of a multiplex circuit (7, 8), and wherein the signals may be connected by means of routes located internally in the component from switch points that are not directly accessible, e.g. points inside the chip (15 to 20) or covered contact points. The device according to the invention is particularly useful for highly integrated semiconductor chips.

Abstract translation: 根据本发明，所述集成电路模块（芯片）（1）一个或多个外部测试连接接触点（垫;销;球），（2，3），其将被测量或待分析的信号（4，5，6） 各自选择性例如 通过多重电路的装置（7,8）经由内部块的传导路径切换通过从立即不可访问电路点，例如 是涵道芯片位置（15到20）或覆盖接触点。 根据本发明的装置特别适用于高集成度的半导体芯片。

公开(公告)号：WO99017125A1

公开(公告)日：1999-04-08

申请号：PCT/US1998/014683

申请日：1998-07-15

IPC: G01R1/06 ,  G01R31/28 ,  G01R31/302 ,  G01R31/303 ,  G01R31/3185 ,  H01J37/305 ,  H01L21/66 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  G01R31/02

CPC classification number: B24B37/013 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/303 ,  G01R31/318505 ,  H01J37/3056 ,  H01J2237/30466 ,  H01L22/26 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method and an apparatus for probing signals from an integrated circuit through the back side of an integrated circuit die (401). A passive diffusion (405) is disposed in a semiconductor substrate of a flip-chip mounted integrated circuit die. The passive diffusion is coupled to a signal line (409) through a contact (407). The signal line carries the integrated circuit signal of interest. In an embodiment, the disclosed passive diffusion is oversized to reduce attenuation of signal acquired from the passive diffusion. In addition, the disclosed passive diffusion is laterally spaced from nearby diffusions in the semiconductor substrate of the integrated circuit to enable exposure of the passive diffusion with a reduced risk of damaging nearby structures in the integrated circuit die, such as for example other diffusions, during the exposing process. Moreover, the disclosed passive diffusion is laterally spaced from nearby diffusions to reduce crosstalk interference from the nearby diffusions.

Abstract translation: 一种用于从集成电路通过集成电路管芯（401）的背面探测信号的方法和装置。 无源扩散（405）设置在倒装芯片安装的集成电路管芯的半导体衬底中。 被动扩散通过触点（407）耦合到信号线（409）。 信号线承载感兴趣的集成电路信号。 在一个实施例中，所公开的被动扩散被超大以减少从被动扩散获得的信号的衰减。 此外，所公开的被动扩散与集成电路的半导体衬底中的附近的扩散横向间隔开，以使被动扩散的曝光降低了集成电路管芯中的附近结构的损害风险，例如其他扩散， 曝光过程。 此外，所公开的被动扩散与附近的扩散横向间隔开，以减少来自附近扩散的串扰干扰。