公开(公告)号：WO2012125610A3

公开(公告)日：2012-12-06

申请号：PCT/US2012028878

申请日：2012-03-13

Applicant: MICRON TECHNOLOGY INC ,  TANG SANH D ,  SILLS SCOTT E ,  WEST WHITNEY L ,  GOODWIN ROB B ,  SINHA NISHANT

Inventor： TANG SANH D ,  SILLS SCOTT E ,  WEST WHITNEY L ,  GOODWIN ROB B ,  SINHA NISHANT

IPC: H01L21/28 ,  H01L21/8239

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：WO2012087578A2

公开(公告)日：2012-06-28

申请号：PCT/US2011063778

申请日：2011-12-07

Applicant: INTEL CORP ,  SIMKA HARSONO S ,  ZIERATH DANIEL J ,  HAVERTY MICHAEL G ,  SHANKAR SADASIVAN

Inventor： SIMKA HARSONO S ,  ZIERATH DANIEL J ,  HAVERTY MICHAEL G ,  SHANKAR SADASIVAN

IPC: H01L21/28 ,  H01L21/31

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

Abstract translation: 提供了用于集成电路的电互连和制造互连的方法。 提供了包括铜互连件的装置，其具有包含银和第二成分（诸如镧，钛，钨，锆，锑或钙）的金属衬里层。 方法包括提供具有在其中形成的沟槽或通孔的衬底，在特征的表面上形成银合金层，其包含银和选自镧，钛，钨，锆，锑和钙的第二组分， 沉积铜种子层，并将铜沉积到特征中。

公开(公告)号：WO2008010371A1

公开(公告)日：2008-01-24

申请号：PCT/JP2007/062140

申请日：2007-06-15

Applicant: 東京エレクトロン株式会社 ,  小島 康彦 ,  池田 太郎 ,  波多野 達夫

Inventor： 小島 康彦 ,  池田 太郎 ,  波多野 達夫

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L23/52

CPC classification number: H01L21/28556 ,  C23C16/0281 ,  C23C16/18 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76877

Abstract: 　有機不純物層の形成を抑え、且つ銅膜と下地となる金属との密着性のよい半導体装置を製造する。 　チタン等の酸化傾向の高い金属からなるバリアメタル層１３（下地膜）が被覆された基板（ウエハＷ）が処理容器内に載置される。水蒸気の供給開始と同時またはその後、銅の有機化合物（例えばＣｕ（ｈｆａｃ）ＴＭＶＳ）からなる原料ガスが供給されて、水蒸気により酸化物層１３ａが形成されたバリアメタル層１３の表面に銅膜が成膜される。次いで、このウエハＷに熱処理を施して、酸化物層１３ａを、バリアメタル層１３を構成する金属と銅との合金層１３ｂに変換する。

Abstract translation: 制造抑制有机杂质层的形成并且对铜膜和作为基底的金属具有优异的粘附性的半导体器件。 在处理室中放置涂覆有由氧化倾向高的金属构成的阻挡金属层（13）（基膜）的基板（晶片（W）），例如钛。 在开始供给水蒸气之后，供给由铜的有机化合物（例如Cu（hfac）TMVS）构成的原料气体，在阻挡金属层的表面上形成铜膜 （13），由此氧化物层（13a）由水蒸气形成。 然后，对晶片（W）进行热处理，将氧化物层（13a）转换成构成阻挡金属层（13）的金属和铜的合金层（13b）。

公开(公告)号：WO02067319A8

公开(公告)日：2004-02-26

申请号：PCT/US0147592

申请日：2001-12-05

Applicant: ASM INT ,  KIM KI-BUM ,  RAAIJMAKERS IVO ,  SOININEN PEKKA J

Inventor： KIM KI-BUM ,  RAAIJMAKERS IVO ,  SOININEN PEKKA J

IPC: C23C16/20 ,  C23C16/34 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film (32) combined with an Al intermediate layer (34) is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract translation: 本发明提供一种制造半导体器件的方法，其可以通过铜互连促进半导体器件的商业化。 在金属互连线制造的过程中，将与Al中间层（34）组合的TiN薄膜（32）用作沟槽或通孔壁上的扩散阻挡层。 为了形成，Al沉积在TiN薄膜上，随后铜填充沟槽。 Al扩散到TiN层并与氧或氮反应，这将有效地吸收晶界，从而阻止铜的扩散。

公开(公告)号：WO00042652A1

公开(公告)日：2000-07-20

申请号：PCT/JP2000/000079

申请日：2000-01-11

IPC: H01L23/522 ,  C23C16/26 ,  H01L21/31 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768

CPC classification number: H01L21/0212 ,  C23C16/26 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76858

Abstract: A wiring layer (34) where wiring lines (35) and recesses (30) between adjacent wiring lines (35) are formed is provided on a first interlayer insulating film (41). A second interlayer insulating film (43) being a CF film made of a filming material such as CF which has poor burying properties is provided on the wiring layer (34). An example of a gas for producing the material is C6F6 gas. A plasma is produced from the gas and the CF film is formed on the wiring layer (34) while preventing any CF film from being buried in the recesses (30). Thus, air gaps (36) each having a shape along the recesses (30) are formed between the wiring lines (35). Such a semiconductor device has a reduced capacitance between wiring lines while the mechanical stress is hardly weakened.

Abstract translation: 在第一层间绝缘膜（41）上设置有在相邻布线（35）之间形成布线（35）和凹部（30）的布线层（34）。 在布线层（34）上设置第二层间绝缘膜（43），其是由诸如CF的成膜材料制成的具有差的掩埋性能的CF膜。 用于生产材料的气体的实例是C 6 F 6气体。 从气体产生等离子体，并且在布线层（34）上形成CF膜，同时防止任何CF膜埋入凹部（30）中。 因此，在布线（35）之间形成有沿着凹部（30）的形状的气隙（36）。 这种半导体器件在布线之间具有减小的电容，同时机械应力几乎不削弱。

公开(公告)号：WO98049718A2

公开(公告)日：1998-11-05

申请号：PCT/IB1998/000368

申请日：1998-03-16

IPC: H01L21/283 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76858 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device with a multilayer wiring (6, 11, 14) with aluminum conductor tracks (7, 12, 15) which are insulated from one another by insulating layers (9, 13). According to the method, an aluminum conductor track (20) provided on a surface (1) of a semiconductor body (2) is covered with a layer of insulating material (21), whereupon a contact window (22) with a wall (23) reaching down to the conductor track is formed in this insulating layer. A conductive intermediate layer (24, 28) and an aluminum layer (25, 29) are provided on this wall, whereupon a heat treatment is carried out such that aluminum (26) grows from the conductor track into the contact window. A conductive intermediate layer of titanium is provided on the wall of the contact window. A very thin, closed aluminum layer, which remains closed also during the heat treatment, can be formed on this titanium layer, which can be provided on the wall with a small thickness. The method is accordingly suitable for making semiconductor devices with multilayer wirings having contact windows of 0.5 mu m or smaller and having aspect ratios above 1.

Abstract translation: 一种具有通过绝缘层（9,13）彼此绝缘的具有铝导体轨道（7,12,15）的多层布线（6,11,14）的半导体器件的制造方法。 根据该方法，设置在半导体主体（2）的表面（1）上的铝导体轨道（20）被绝缘材料层（21）覆盖，然后将具有壁（23）的接触窗口（22） ）形成在该绝缘层上。 在该壁上设置导电中间层（24,28）和铝层（25,29），由此进行热处理，使得铝（26）从导体轨迹生长到接触窗口中。 导电中间层的钛提供在接触窗的壁上。 可以在该钛层上形成非常薄的封闭的铝层，其在热处理期间保持闭合，该钛层可以在壁上设置较小的厚度。 因此，该方法适用于制造具有接触窗口为0.5μm或更小并具有高于1的纵横比的具有多层布线的半导体器件。

公开(公告)号：WO2017146713A1

公开(公告)日：2017-08-31

申请号：PCT/US2016/019617

申请日：2016-02-25

Applicant: INTEL CORPORATION

Inventor： JEZEWSKI, Christopher J. ,  CHEBIAM, Ramanan V. ,  CHAWLA, Jasmeet S. ,  KOBRINSKY, Mauro J. ,  CLARKE, James S.

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/28 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238

Abstract: A conductive connector for a microelectronic structure may be formed in an opening in a dielectric layer, wherein a ruthenium/aluminum-containing liner is disposed between the dielectric layer and a substantially aluminum-free copper fill material within the opening. The ruthenium/aluminum-containing liner may be formed by depositing a ruthenium-containing liner and migrating aluminum into the ruthenium-containing liner with an annealing process. The aluminum may be presented as a layer formed either before or after the deposition of a copper fill material, or may be presented within a copper/aluminum alloy fill material wherein the annealing process migrates the aluminum out of the copper/aluminum alloy and into the ruthenium-containing liner.

Abstract translation: 用于微电子结构的导电连接器可以形成在介电层的开口中，其中含钌/铝的衬垫设置在介电层和基本上不含铝的铜填充材料之间 开幕。 含钌/铝的衬里可以通过沉积含钌衬里并通过退火工艺将铝迁移到含钌衬里中来形成。 铝可以呈现为在铜填充材料的沉积之前或之后形成的层，或者可以呈现在铜/铝合金填充材料内，其中退火过程将铝迁移出铜/铝合金并且进入 含钌衬垫。

公开(公告)号：WO2012125610A2

公开(公告)日：2012-09-20

申请号：PCT/US2012/028878

申请日：2012-03-13

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

Inventor： TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

IPC: H01L21/28 ,  H01L21/8239

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 为半导体结构和存储单元形成诸如互连和电极之类的导电元件的方法。 该方法包括在至少一个开口的一部分中形成包含银的第一导电材料和第二导电材料，并执行抛光工艺以用第一导电材料和第二导电材料中的至少一个填充该至少一个开口。 可以执行退火工艺以形成银和材料的混合物或合金。 该方法能够形成尺寸减小（例如，小于约20nm）的含银导电元件。 所得的导电元件具有理想的电阻率。 例如，该方法可用于形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了包括这种导电结构的半导体结构和存储单元。

公开(公告)号：WO2012040734A2

公开(公告)日：2012-03-29

申请号：PCT/US2011053322

申请日：2011-09-26

Applicant: INTEL CORP ,  AKOLKAR ROHAN N ,  BALAKRISHNAN SRIDHAR ,  CLARKE JAMES S ,  JEZEWSKI CHRISTOPHER J ,  YASHAR PHILIP

Inventor： AKOLKAR ROHAN N ,  BALAKRISHNAN SRIDHAR ,  CLARKE JAMES S ,  JEZEWSKI CHRISTOPHER J ,  YASHAR PHILIP

IPC: H01L21/28 ,  H01L21/3205

CPC classification number: C25D5/02 ,  C23C28/023 ,  C25D7/123 ,  H01L21/76831 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/12361 ,  Y10T428/12389 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

公开(公告)号：WO2009117670A3

公开(公告)日：2012-03-22

申请号：PCT/US2009037826

申请日：2009-03-20

Applicant: HARVARD COLLEGE ,  GORDON ROY GERALD ,  KIM HOON

Inventor： GORDON ROY GERALD ,  KIM HOON

IPC: H01L21/768 ,  C23C16/16 ,  C23C16/18 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76864 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate (80) and manganese silicon nitride layers (60,90) that completely surrounds copper wires (20,120) in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper- manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese - containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract translation: 用于集成电路的互连结构包括在集成电路中完全围绕铜线（20,120）的硅酸锰（80）和锰氮化硅层（60,90）及其制造方法。 硅酸锰形成阻止铜从电线中扩散的屏障，从而保护绝缘体免于过早击穿，并保护晶体管免受铜的退化。 硅酸锰和氮化硅锰也促进了铜和绝缘体之间的强粘附，从而在制造和使用期间保持了器件的机械完整性。 铜锰硅酸盐和锰氮化硅界面处的强粘附性也可防止在使用设备期间铜的电迁移而导致故障。 含锰护套还可以保护铜免受氧气或水从其周围的腐蚀。