公开(公告)号：WO2018174967A1

公开(公告)日：2018-09-27

申请号：PCT/US2017/063685

申请日：2017-11-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： MORI, Yoshio

IPC: H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/249 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L45/1233 ,  H01L45/1608

Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

公开(公告)号：WO2018067250A1

公开(公告)日：2018-04-12

申请号：PCT/US2017/049445

申请日：2017-08-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  ALSMEIER, Johann ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul ,  KAI, James

IPC: H01L27/1158 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7926

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

Abstract translation: 在衬底上形成包括绝缘层和牺牲材料层的交替堆叠的层堆叠。 在形成存储器堆叠结构之后，通过层堆叠形成背侧沟槽。 牺牲材料层被导电层替代。 在形成导电层之后，通过叠层的漏极选择层形成漏极选择层电介质隔离结构。 漏极选择层电介质隔离结构横向分隔用作存储器堆叠结构的漏极选择电平栅极电极的导电层部分。

公开(公告)号：WO2017213721A1

公开(公告)日：2017-12-14

申请号：PCT/US2017/019132

申请日：2017-02-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： YU, Jixin ,  LU, Zhenyu ,  CHU, Alexander ,  YAMAGUCHI, Kensuke ,  OGAWA, Hiroyuki ,  MAO, Daxin ,  LI, Yan ,  ALSMEIER, Johann

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

Abstract translation: 半导体结构包括位于衬底上的存储器级组件，并包括至少一个交替堆叠和垂直延伸穿过所述至少一个交替堆叠的存储器堆叠结构。 所述至少一个交替堆叠中的每一个包括各自的绝缘层和相应的导电层的交替层，并且所述至少一个交替堆叠中的每个导电层包括相应的开口，使得相应的间隔物电介质部分 位于开口中接触相应导电层的侧壁。 至少一个贯穿存储器层的通孔结构垂直延伸穿过每个间隔物介电部分和绝缘层。

公开(公告)号：WO2017091275A1

公开(公告)日：2017-06-01

申请号：PCT/US2016/050432

申请日：2016-09-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： NISHIKAWA, Masatoshi ,  MIYAMOTO, Masafumi ,  OGAWA, Hiroyuki

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.

Abstract translation: 可以在绝缘层和字线的交替堆叠内提供分裂存储器单元。 通过限制单词水平内的隔离器绝缘体结构的水平，可以提供至少一个下部选择栅极级导电层和/或至少一个没有分裂存储器单元配置的上部选择级导电层 线。 至少一个蚀刻停止层可以形成在至少一个下选择栅极级间隔物材料层的上方。 在至少一个蚀刻停止层上形成交替的绝缘层和间隔材料层的叠层。 通过采用蚀刻停止层作为阻挡结构的交替堆叠形成隔离器绝缘体结构。 随后可以形成上部选择的间隔物材料层。 间隔材料层和选择层材料层形成为导电层，或者用导电层代替。

公开(公告)号：WO2017091274A1

公开(公告)日：2017-06-01

申请号：PCT/US2016/050427

申请日：2016-09-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： NISHIKAWA, Masatoshi ,  MIYAMOTO, Masafumi ,  KAI, James

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847

Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.

Abstract translation: 在衬底上形成交替堆叠的牺牲材料层和绝缘层。 可以使用开口的子集来执行用导电层替换牺牲材料层。 采用开口的主要子集来在其中形成存储器堆叠结构。 使用少量的开口子集作为进入开口，用于引入蚀刻剂以去除牺牲材料层以形成横向凹陷并提供用于在横向凹陷中沉积导电层的反应物。 通过将开口分布在整个开口上并且不需要采用背侧沟槽来替换牺牲材料层，背侧沟槽的尺寸和横向范围可以减小到足以仅容纳背侧接触过孔结构的水平。

公开(公告)号：WO2017074574A1

公开(公告)日：2017-05-04

申请号：PCT/US2016/051355

申请日：2016-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LIU, Jin ,  GE, Chun ,  ALSMEIER, Johann

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line (WLL) and dielectric layers (DL) above a substrate (510), forming a source line (514) above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element (516a-c) on the substrate adjacent to the memory hole.

Abstract translation: 提供了一种制造单片三维存储器结构的方法。 该方法包括在衬底（510）上方形成交替字线（WLL）和电介质层（DL）的堆叠，在衬底上方形成源极线（514），形成延伸穿过交替字线和电介质层 和源极线，并且在衬底上与存储器孔相邻地形成机械支撑元件（516a-c）。

公开(公告)号：WO2017065869A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/047397

申请日：2016-08-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  MAKALA, Raghuveer S. ,  LIU, Jin ,  CHOWDHURY, Murshed ,  LEE, Yao-sheng ,  ALSMEIER, Johann

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.

Abstract translation: 包括多个堆叠结构的三维存储器件可以形成有接合区域电极，该接合区域电极是形成在位于上部堆叠结构与下部堆叠结构之间的接口附近的接合区域处的电极 。 存储器堆栈结构通过多个堆栈结构形成。 接合区域电极在不同堆叠结构之间的界面附近侧向包围存储器堆叠结构的一部分。 接合区域电极包括具有厚度的层部分和侧向围绕存储器堆叠结构并且具有比层部分的厚度更大的垂直长度的套环部分。 相对于层部分的垂直范围而言，凸缘部分的增加的垂直范围提供对存储器堆叠结构中位于不同堆叠结构之间的界面附近的半导体沟道的一部分的增强控制。

公开(公告)号：WO2017034647A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/036724

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LU, Zhenyu ,  CHIEN, Henry ,  ALSMEIER, Johann ,  MIYATA, Koji ,  ZHANG, Tong ,  MUI, Man ,  KAI, James ,  SHI, Wenguang ,  WEI, Zhao ,  HU, Xiaolong ,  XU, Jiyin ,  HEMINK, Gerrit Jan ,  PETTI, Christopher

IPC: H01L27/115

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66666 ,  H01L29/7883 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Abstract translation: 多层存储器件形成在衬底上，使得存储器堆叠结构延伸穿过绝缘层的交替堆叠和每层内的导电层。 位线形成在具有半导体通道上的漏极区域的底层和在半导体通道下方具有漏极区域的上层，使得位线在下层和上覆层之间共享。 可以在每个层上形成源极线，其中源极区域覆盖半导体沟道和漏极区域。 如果源线上方存在另一层，则可以在两个垂直相邻层之间共享源线。

公开(公告)号：WO2017034646A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/036656

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LU, Zhenyu ,  MAO, Daxin ,  MIYATA, Koji ,  ARIYOSHI, Junichi ,  ALSMEIER, Johann ,  MATAMIS, George ,  SHI, Wenguang ,  XU, Jiyin ,  HU, Xiaolong ,  LIN, Andrew ,  YU, Jixin

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.

Abstract translation: 提供一种制造存储器件的方法。 该方法包括在半导体衬底上形成绝缘体层和隔离材料层的第一交替叠层，蚀刻第一交替堆叠以暴露单晶半导体材料，在单晶半导体材料上形成第一外延半导体基座，使得第一 外延半导体基座与单晶半导体材料进行外延对准，通过第一交替叠层形成存储堆栈结构的阵列，并在第一外延半导体基座上形成至少一个半导体器件。

公开(公告)号：WO2016178392A1

公开(公告)日：2016-11-10

申请号：PCT/JP2016/063074

申请日：2016-04-26

Applicant: 株式会社フローディア

Inventor： 大和田　福夫 ,  川嶋　泰彦 ,  吉田　信司 ,  谷口　泰弘 ,  奥山　幸祐

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

Abstract: 第1選択ゲート電極（DG）と第2選択ゲート電極（SG）とを、メモリゲート構造体（4）の側壁に沿ってサイドウォール状に形成したことから、第1選択ゲート電極（DG）および第2選択ゲート電極（SG）がメモリゲート構造体（4）上に乗り上げずに、メモリゲート構造体（4）、第1選択ゲート構造体（5）および第2選択ゲート構造体（6）の高さを揃えることができ、その分、従来よりも小型化を図り得、また、第1選択ゲート電極（DG）上のシリサイド層（S1）や、第2選択ゲート電極（SG）上のシリサイド層（S2）をキャップ膜（CP1）の膜厚分だけメモリゲート電極（MG）から遠ざけることができるので、メモリゲート電極（MG）に対して、第1選択ゲート電極（DG）上および第2選択ゲート電極（SG）上のシリサイド層（S1,S2）が接触し難くなり、その分、メモリゲート電極（MG）のショート不良を防止し得る、半導体集積回路装置、および半導体集積回路装置の製造方法を提案する。

Abstract translation: 提供半导体集成电路器件和半导体集成电路器件的制造方法。 在半导体集成电路器件中，第一选择栅电极（DG）和第二选择栅电极（SG）沿着存储栅结构（4）的侧面形成为侧壁的形状，并且存储栅的高度 结构（4），第一选择栅极结构（5）和第二选择栅极结构（6）可以在不将第一选择栅电极（DG）和第二选择栅电极（SG）安装在存储栅结构 （4）。 因此，可以实现比以往更大的尺寸减小。 此外，由于第一选择栅电极（DG）上的硅化物层（S1）或第二选择栅电极（SG）上的硅化物层（S2）可以远离存储栅电极（MG）远离等距 对于膜膜（CP1）的膜厚度，第一选择栅电极（DG）和第二选择栅电极（SG）上的硅化物层（S1，S2）难以与存储栅电极 ）。 因此，可以防止存储栅电极（MG）的短路故障。