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    LOGIC ARRANGEMENT
    2.
    发明申请
    LOGIC ARRANGEMENT 审中-公开
    逻辑安排

    公开(公告)号：WO2013160709A2

    公开(公告)日：2013-10-31

    申请号：PCT/HU2013/000036

    申请日：2013-04-26

    Applicant: BUDAPESTI MÜSZAKI ÉS GAZDASÁGTUDOMÁNYI EGYETEM ,  UNIVERSITY OF OULU

    Inventor： MIZSEI, János ,  LAPPALAINEN, Jyrki

    IPC: H03K19/02

    CPC classification number: H03K19/02 ,  H03K19/20

    Abstract: The invention is a logic arrangement comprising a thermoconductive element (10) having two states according to its electric resistance and being switchable between the two states by a thermal energy amount, and a heating resistor (12', 12", 12"') being coupled by energy coupling to the thermoconductive element (10) and being adapted for generating thermal energy. In the logic arrangement, the heating resistor (12', 12", 12"') is a logic input (16', 16", 16"') of a logic level determined by the thermal energy amount thereon, and the thermoconductive element (10) is a logic output (14) of a logic level determined by the thermal energy amount thereon.

    Abstract translation: 本发明是包括根据其电阻具有两种状态的热传导元件（10）并且可以通过热能量在两种状态之间切换的热传导元件（10），以及加热电阻器（12'，12“，12”'） 通过能量耦合耦合到热传导元件（10）并适于产生热能。 在逻辑布置中，加热电阻器（12'，12“，12”'）是由其上的热能量确定的逻辑电平的逻辑输入（16'，16“，16”'），并且导热元件 （10）是由其上的热能量确定的逻辑电平的逻辑输出（14）。

    DEVICE AND METHOD FOR DUAL-MODE LOGIC
    3.
    发明申请
    DEVICE AND METHOD FOR DUAL-MODE LOGIC 审中-公开
    双模逻辑的装置和方法

    公开(公告)号：WO2013018061A1

    公开(公告)日：2013-02-07

    申请号：PCT/IB2012/053972

    申请日：2012-08-02

    Applicant: BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY ,  FISH, Alexander ,  KAIZERMAN, Asaf ,  FISHER, Sagi ,  LEVY, Itamar

    Inventor： FISH, Alexander ,  KAIZERMAN, Asaf ,  FISHER, Sagi ,  LEVY, Itamar

    IPC: H03K19/088 ,  H03K19/02 ,  H03K19/00

    CPC classification number: G06F17/5045 ,  G06F9/3869 ,  G06F17/50 ,  G06F17/505 ,  G06F2217/02 ,  H03K19/02 ,  H03K19/094 ,  H03K19/20

    Abstract: A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element.

    Abstract translation: 用于在静态和动态模式中的任意一种可选择操作的双模逻辑门包括：静态门，其包括至少一个逻辑输入和逻辑输出; 模式选择器，被配置为输出关闭信号以选择静态模式操作并输出动态时钟信号以选择动态模式操作; 以及与模式选择器静态门相关联的开关元件，包括连接到恒定电压的第一输入端，用于从模式选择器输入模式选择信号的第二输入端和连接到静态门极逻辑输出端的输出端。 开关元件通过将适当的信号施加到开关元件来将逻辑门操作从静态切换到动态模式。

    APPARATUS AND ASSOCIATED METHODS IN RELATION TO CARBON NANOTUBE NETWORKS
    4.
    发明申请
    APPARATUS AND ASSOCIATED METHODS IN RELATION TO CARBON NANOTUBE NETWORKS 审中-公开
    关于碳纳米管网络的装置和相关方法

    公开(公告)号：WO2010142840A1

    公开(公告)日：2010-12-16

    申请号：PCT/FI2010/050306

    申请日：2010-04-15

    Applicant: NOKIA CORPORATION ,  PASANEN, Pirjo ,  SEPPÄLÄ, Eira ,  OKSANEN, Markku ,  ERMOLOV, Vladimir

    Inventor： PASANEN, Pirjo ,  SEPPÄLÄ, Eira ,  OKSANEN, Markku ,  ERMOLOV, Vladimir

    IPC: H01L51/10 ,  B82B1/00 ,  H03K19/02

    CPC classification number: H01L51/0558 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0545

    Abstract: In one or more embodiments described herein, there is provided an apparatus (200) comprising a substrate (201 ), and a plurality of carbon nanotubes (semiconducting nano-elements) disposed and fixed with said substrate (201 ). The nanotubes are disposed and fixed on said substrate such that they define a carbon nanotube network (202) substantially at the percolation threshold of the network. As the network (202) is at the percolation threshold, this provides for one or more signal paths extending from an input region (203b) to an output region (204b). The apparatus is configured to, upon receiving particular input signalling via the input region (203b), provide particular predefined output signalling at the output (204b) via the one or more signal paths, the particular output signalling being predefined according to the one or more one signal paths.

    Abstract translation: 在本文所述的一个或多个实施例中，提供了一种包括衬底（201）和与所述衬底（201）布置和固定的多个碳纳米管（半导体纳米元件）的设备（200）。 纳米管被布置和固定在所述基板上，使得它们基本上限定在网络的渗透阈值处的碳纳米管网络（202）。 当网络（202）处于渗透阈值时，这提供从输入区域（203b）延伸到输出区域（204b）的一个或多个信号路径。 该装置被配置为在经由输入区域（203b）接收到特定的输入信号后，经由一个或多个信号路径在输出（204b）处提供特定的预定义的输出信令，该特定的输出信号是根据一个或多个 一个信号路径。

    LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS
    6.
    发明申请
    LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS 审中-公开
    电路各个电子部件，操作方法有关步骤的加法二进制数的应用

    公开(公告)号：WO99012212A2

    公开(公告)日：1999-03-11

    申请号：PCT/DE1998/002521

    申请日：1998-08-26

    IPC: G06F7/501 ,  G06F7/50 ,  G06F7/505 ,  H01L29/66 ,  H03K17/00 ,  H03K19/02 ,  H01L29/76

    CPC classification number: G06F7/505 ,  G06F7/502 ,  G06F2207/4828 ,  H03K19/02 ,  Y10S977/89 ,  Y10S977/937 ,  Y10S977/94

    Abstract: A circuit arrangement with lone-electron components has at least one lone-electron transistor, which is placed between a first main node and a second main node. The first node is capacitive betweeen a first operating voltage tap and a second operating voltage tap. The gate electrode of the lone-electron transistor is connected to a control voltage tap. The circuit arrangement concerned is suited for the logical combination of binary numbers, the positions of which are recorded in the first and second main nodes.

    Abstract translation: 在具有单电子部件的电路布置中，至少一个单电子晶体管，其连接第一主节点和第二主节点之间。 第一主节点是第一电源电压端子和第二操作电压端子之间连接的电容。 单电子晶体管的栅电极被连接到控制电压端子。 该电路装置适合于二进制数，其数字被存储在第一和第二主节点的逻辑连接。

    QUASI-ADIABATIC LOGIC CIRCUITS
    7.
    发明申请
    QUASI-ADIABATIC LOGIC CIRCUITS 审中-公开

    公开(公告)号：WO2019217566A1

    公开(公告)日：2019-11-14

    申请号：PCT/US2019/031338

    申请日：2019-05-08

    Applicant: AGAN, Tommy, Allen ,  LUPINO, James, John

    Inventor： AGAN, Tommy, Allen ,  LUPINO, James, John

    IPC: H03B11/10 ,  H03K19/017 ,  H03K19/02 ,  H03K19/094 ,  H03K19/096 ,  H03K19/20 ,  H03K19/12

    Abstract: Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives sinusoidal power. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the sinusoidal supply signal. Such a sinusoidal transient switching portion of the signal has lower frequency components than have traditional CMOS logic gate transients. Some embodiments include an inductor through which the sinusoidal supply signal is provided to the quasi-adiabatic logic gate. Such an inductor can both provide charge to and recover charge from switching quasi-adiabatic logic gates, thereby further reducing power.

    DUAL ELECTRO-MECHANICAL OSCILLATOR FOR DYNAMICALLY REPROGRAMMABLE LOGIC GATE
    8.
    发明申请
    DUAL ELECTRO-MECHANICAL OSCILLATOR FOR DYNAMICALLY REPROGRAMMABLE LOGIC GATE 审中-公开

    公开(公告)号：WO2018193378A1

    公开(公告)日：2018-10-25

    申请号：PCT/IB2018/052665

    申请日：2018-04-17

    Applicant: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： NANAIAH, Karumbaiah Chappanda ,  YOUNIS, Mohammad Ibrahim

    IPC: H03K19/02 ,  H03H9/02

    Abstract: Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro- cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

    NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS
    9.
    发明申请
    NANO-ELECTRO-MECHANICAL-SWITCH ADIABATIC DYNAMIC LOGIC CIRCUITS 审中-公开
    纳米电子机械开关ADIABATIC动态逻辑电路

    公开(公告)号：WO2014033567A1

    公开(公告)日：2014-03-06

    申请号：PCT/IB2013056276

    申请日：2013-07-31

    Applicant: IBM ,  IBM JAPAN ,  IBM RES GMBH

    Inventor： DESPONT MICHEL ,  GROGG DANIEL ,  HAGLEITNER CHRISTOPH ,  PU YU

    IPC: H03K19/02

    CPC classification number: H03K19/02 ,  H03K19/20

    Abstract: The invention refers to a dynamic logic gate comprising a nano-electro-mechanical- switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.

    Abstract translation: 本发明涉及一种包括纳米机电开关，优选四端子纳米机电开关的动态逻辑门。 本发明还涉及包括这种动态逻辑门的动态逻辑级联电路。 特别地，本发明的实施例涉及包括单轨或双轨动态逻辑门的动态逻辑级联电路。

    SYSTEMS AND METHODS FOR ASYNCHRONOUS HANDSHAKE-BASED INTERCONNECTS
    10.
    发明申请
    SYSTEMS AND METHODS FOR ASYNCHRONOUS HANDSHAKE-BASED INTERCONNECTS 审中-公开
    用于基于异步通信系统的互连的系统和方法

    公开(公告)号：WO2013044135A3

    公开(公告)日：2013-05-16

    申请号：PCT/US2012056714

    申请日：2012-09-21

    Applicant: QUALCOMM INC ,  VENKATRAMAN SUBRAMANIAM ,  LEVIN JEFFREY ALEXANDER

    Inventor： VENKATRAMAN SUBRAMANIAM ,  LEVIN JEFFREY ALEXANDER

    IPC: G06F1/12 ,  H03K19/02 ,  H04L25/40

    CPC classification number: G06F1/12

    Abstract: Certain aspects of the present disclosure provides techniques for a handshaking protocol, and corresponding circuit elements, for an asynchronous network. The techniques utilize a clock-less delay insensitive data encoding scheme. The proposed network may operate correctly regardless of the delay in the interconnecting wires.

    Abstract translation: 本公开的某些方面提供了用于异步网络的握手协议和对应的电路元件的技术。 该技术利用无时钟的延迟不敏感数据编码方案。 所提出的网络可以正确地操作，而不管互连线中的延迟如何。

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