公开(公告)号：WO2023077264A1

公开(公告)日：2023-05-11

申请号：PCT/CN2021/128164

申请日：2021-11-02

Applicant: 中国科学院微电子研究所

Inventor： 张刚 ,  李春龙 ,  霍宗亮 ,  叶甜春

IPC: H01L23/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  G11C16/04 ,  G11C16/26

Abstract: 本公开提供了一种存储单元，包括：沟道层阵列，包括：N个沟道层，N个沟道层沿着第一方向垂直设置在衬底上，N个沟道层外侧依次设置隧穿层及存储层，N为正整数；N个导热芯，分别位于N个沟道层内，且贯穿衬底；热偶阵列，包括：沿着第一方向的负方向生长在衬底上的热偶字线层及位于热偶字线层上的N个热偶层，N个热偶层与N个导热芯一一对应连接；其中，在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，使与该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。本公开还提供了一种三维存储器及其操作方法。

公开(公告)号：WO2023075857A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/029336

申请日：2022-05-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TOBIOKA, Akihiro ,  TANAKA, Yusuke

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings and support openings are formed through the alternating stack. The memory openings are arranged in a first hexagonal array having a nearest-neighbor direction that is parallel to a first horizontal direction, and the support openings are arranged in a second hexagonal array having a nearest-neighbor direction that is perpendicular to the first horizontal direction. Memory opening fill structures are formed within a respective one of the memory openings, and support pillar structures within a respective one of the support openings.

公开(公告)号：WO2023069149A1

公开(公告)日：2023-04-27

申请号：PCT/US2022/028469

申请日：2022-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TSUTSUMI, Masanori ,  MUKAE, Yusuke ,  HINOUE, Tatsuya ,  KASAI, Yuki

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

公开(公告)号：WO2023034103A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/041449

申请日：2022-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FUKUZUMI, Yoshiaki ,  FUJIKI, Jun ,  TANAKA, Shuji ,  SAITO, Masanobu

IPC: H01L27/11526 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, and a second field-effect transistor between the data line and a second string of series-connected memory cells, wherein a control gate of the first field-effect transistor is connected to a control gate of the second field-effect transistor, and wherein a channel of the first field-effect transistor was fabricated to have a first threshold voltage and a channel of the second field-effect transistor was fabricated to have a second threshold voltage, different than the first threshold voltage.

公开(公告)号：WO2023033338A1

公开(公告)日：2023-03-09

申请号：PCT/KR2022/009871

申请日：2022-07-07

Applicant: 한양대학교 산학협력단

Inventor： 송윤흡

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11597 ,  H01L27/1159 ,  G11C16/10 ,  G11C16/08 ,  G11C16/30 ,  G11C16/04 ,  H01L27/11585

Abstract: 강유전체 기반의 3차원 플래시 메모리가 개시된다. 복수의 메모리 셀들 중 프로그램 동작의 대상이 되는 대상 메모리 셀에 인가하는 프로그램 전압을 음의 범위 값 또는 양의 범위 범위 값에서 결정하여, 대상 메모리 셀에 대응하는 데이터 저장 패턴의 일부 영역의 분극 전하량을 변화시켜 대상 메모리 셀에 대한 다치화를 구현하는 것을 특징으로 한다. 또한 수직 채널 패턴은 기판이 N타입으로 형성됨에 따라 P타입인 것을 특징으로 한다.

公开(公告)号：WO2023021752A1

公开(公告)日：2023-02-23

申请号：PCT/JP2022/010073

申请日：2022-03-08

Applicant: キオクシア株式会社

Inventor： 池上　一隆 ,  滋賀　秀裕 ,  中澤　新悟

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  H01L21/336 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792

Abstract: メモリシステムにおける読み出し動作の低消費電力化及び高速化を実現するためのメモリシステムは、ソース線と、ｊ層のストリング選択線と、ｉ層の第１ワード線と、ｉ層の第２ワード線と、２ｎ個に分離された１層のセレクトゲート線と、複数のメモリピラーと、制御回路と、を有する。複数のメモリピラーの各々は、第１ストリングと第２ストリングとを有する。第１ストリングは、第１トランジスタ、ｉ個の第１メモリセル、及びｊ個の第２メモリセルを有し、第１トランジスタ、ｉ個の第１メモリセル、及びｊ個の第２メモリセルは電気的に直列に接続される。第２ストリングは、第２トランジスタ、ｉ個の第３メモリセル、及びｊ個の第４メモリセルを有し、第２トランジスタ、ｉ個の第３メモリセル、及びｊ個の第４メモリセルは電気的に直列に接続される。第２メモリセル及び第４メモリセルにおいて、ｊはｎ以下である。

公开(公告)号：WO2023014463A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/036454

申请日：2022-07-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GUPTA, Sidhartha ,  KAUSHIK, Naveen ,  SHARMA, Pankaj

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel- material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void- space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：WO2023004264A1

公开(公告)日：2023-01-26

申请号：PCT/US2022/073774

申请日：2022-07-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SCARBROUGH, Alyssa N. ,  WANG, Yiping ,  GREENLEE, Jordan D. ,  HOPKINS, John

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：WO2023287488A1

公开(公告)日：2023-01-19

申请号：PCT/US2022/030489

申请日：2022-05-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： XU, Lifang ,  CHARY, Indra, V. ,  WELLS, David, H. ,  JAIN, Harsh, Narendrakumar ,  MEOTTO, Umberto, Maria ,  TESSARIOL, Paolo

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：WO2022267007A1

公开(公告)日：2022-12-29

申请号：PCT/CN2021/102384

申请日：2021-06-25

Applicant: INTEL CORPORATION ,  HUANG, Guangyu ,  BASU, Dipanjan ,  KUO, Meng-Wei ,  KOVAL, Randy ,  MEBRAHTU, Henok ,  WANG, Minsheng ,  LI, Jie ,  WANG, Fei ,  GAO, Qun ,  ZHANG, Xingui ,  LI, Guanjie

Inventor： HUANG, Guangyu ,  BASU, Dipanjan ,  KUO, Meng-Wei ,  KOVAL, Randy ,  MEBRAHTU, Henok ,  WANG, Minsheng ,  LI, Jie ,  WANG, Fei ,  GAO, Qun ,  ZHANG, Xingui ,  LI, Guanjie

IPC: H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7923

Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.