公开(公告)号：EP1734579A3

公开(公告)日：2008-09-03

申请号：EP06012323.9

申请日：2006-06-14

申请人： Sanyo Electric Co., Ltd.

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/485

CPC分类号： H01L23/3192 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode (4) formed on a semiconductor substrate (1), a first passivation film (5) covering an end portion of the pad electrode (4) and having a first opening (6) on the pad electrode (4), a plating layer (7) formed on the pad electrode (4) in the first opening (6), a second passivation film (9) covering an exposed portion of the pad electrode (4) between an end portion of the first passivation film (5) and the plating layer (7), covering an end portion of the plating layer (7), and having a second opening (10) on the plating layer (7), and a conductive terminal (11) formed on the plating layer (7) in the second opening (10).

公开(公告)号：EP1505643A3

公开(公告)日：2009-05-06

申请号：EP04018715.5

申请日：2004-08-06

申请人： SANYO ELECTRIC CO., LTD.

发明人： Noma, Takashi ,  Kitagawa, Katsuhiko ,  Otsuka, Hisao ,  Suzuki, Akira ,  Seki, Yoshinori ,  Takao,Yukihiro ,  Yamaguchi, Keiichi ,  Wakui, Motoaki ,  Iida, Masanori

IPC分类号： H01L23/31 ,  H01L21/68

CPC分类号： H01L24/13 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window (20) to expose first wirings (3) is formed only in a region of a semiconductor substrate (1) where the first wirings (3) exist. As a result, area of the semiconductor substrate (1) bonded to a supporting body (4) through an insulation film (2) and a resin (5) is increased to prevent cracks in the supporting body (4) and separation of the semiconductor substrate (1) from the supporting body (4). A slit (30) is formed along a dicing line after forming the window (20), the slit (30) is covered with a protection film (10) and then the semiconductor substrate (1) is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.

摘要翻译： 以芯片尺寸封装形成的半导体器件的制造方法被改进以提高产量和可靠性。 仅在半导体衬底（1）的存在第一布线（3）的区域中形成暴露第一布线（3）的窗口（20）。 结果，通过绝缘膜（2）和树脂（5）结合到支撑体（4）的半导体衬底（1）的面积增加，以防止支撑体（4）中的裂缝和半导体 衬底（1）与支撑体（4）分离。 在形成窗口（20）之后沿切割线形成狭缝（30），用保护膜（10）覆盖狭缝（30），然后将半导体衬底（1）切割成单独的半导体管芯。 因此，可防止切割表面或半导体管芯的边缘处的分离，否则将由切割中的刀片的接触引起。

公开(公告)号：EP1777740A2

公开(公告)日：2007-04-25

申请号：EP06020446.8

申请日：2006-09-28

申请人： Sanyo Electric Co., Ltd.

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/31 ,  H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/562 ,  H01L23/564 ,  H01L2221/6834 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16237 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/00014

摘要： The invention prevents a pad electrode (3) for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode (3) connected to the electronic circuit, and a second pad electrode (4) connected to the first pad electrode (3) are formed on a semiconductor substrate (1). A first protection film (5) is formed, covering the first pad electrode (3) and having an opening on the second pad electrode (4) only. A wiring layer (10) is further formed, being connected to the back surface of the first pad electrode (3) through a via hole penetrating the semiconductor substrate (1) and extending from the via hole onto the back surface of the semiconductor substrate (1).

摘要翻译： 本发明防止半导体器件的外部连接的焊盘电极（3）被损坏。 连接到电子电路的电子电路，第一焊盘电极（3）和连接到第一焊盘电极（3）的第二焊盘电极（4）形成在半导体衬底（1）上。 形成第一保护膜（5），仅覆盖第一焊盘电极（3）并且在第二焊盘电极（4）上具有开口。 进一步形成布线层（10），其通过贯穿半导体基板（1）的通路孔与第一焊盘电极（3）的背面连接并从通孔延伸到半导体基板的背面 1）。

公开(公告)号：EP1505643A2

公开(公告)日：2005-02-09

申请号：EP04018715.5

申请日：2004-08-06

申请人： Sanyo Electric Co., Ltd.

发明人： Noma, Takashi ,  Kitagawa, Katsuhiko ,  Otsuka, Hisao ,  Suzuki, Akira ,  Seki, Yoshinori ,  Takao,Yukihiro ,  Yamaguchi, Keiichi ,  Wakui, Motoaki ,  Iida, Masanori

IPC分类号： H01L23/31 ,  H01L21/68

CPC分类号： H01L24/13 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window (20) to expose first wirings (3) is formed only in a region of a semiconductor substrate (1) where the first wirings (3) exist. As a result, area of the semiconductor substrate (1) bonded to a supporting body (4) through an insulation film (2) and a resin (5) is increased to prevent cracks in the supporting body (4) and separation of the semiconductor substrate (1) from the supporting body (4). A slit (30) is formed along a dicing line after forming the window (20), the slit (30) is covered with a protection film (10) and then the semiconductor substrate (1) is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.

摘要翻译： 改善了以芯片尺寸封装形成的半导体器件的制造方法，以提高产量和可靠性。 仅在存在第一配线（3）的半导体衬底（1）的区域中形成用于露出第一配线（3）的窗口（20）。 结果，增加了通过绝缘膜（2）和树脂（5）接合到支撑体（4）的半导体衬底（1）的面积，以防止支撑体（4）中的裂纹和半导体的分离 基板（1）从支撑体（4）。 在形成窗（20）之后，沿着切割线形成狭缝（30），用保护膜（10）覆盖狭缝（30），然后将半导体基板（1）切割成单独的半导体管芯。 因此，可以防止在切割时由刀片接触而导致的半导体管芯的切割面或边缘处的分离。

公开(公告)号：EP1505643B1

公开(公告)日：2012-11-14

申请号：EP04018715.5

申请日：2004-08-06

申请人： SANYO ELECTRIC CO., LTD.

发明人： Noma, Takashi ,  Kitagawa, Katsuhiko ,  Otsuka, Hisao ,  Suzuki, Akira ,  Seki, Yoshinori ,  Takao,Yukihiro ,  Yamaguchi, Keiichi ,  Wakui, Motoaki ,  Iida, Masanori

IPC分类号： H01L23/31 ,  H01L21/68

CPC分类号： H01L24/13 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

公开(公告)号：EP1737036A2

公开(公告)日：2006-12-27

申请号：EP06012324.7

申请日：2006-06-14

申请人： Sanyo Electric Co., Ltd

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention provides a CSP type semiconductor device with high reliability.
The semiconductor device includes a pad electrode (4) formed on a semiconductor substrate (1) with insulation films (2, 3) interposed therebetween, a plating layer (7) formed on the pad electrode (4), a conductive terminal (9) formed on the plating layer and electrically connected with the pad electrode (4), and a first passivation film (5) covering the insulation films (2, 3) and a side end portion of the pad electrode (4), in which an exposed portion of the pad electrode (4) that causes corrosion is covered by forming a second passivation film (10) so as to cover the first passivation film (5), the plating layer (7), and a portion of a sidewall of the conductive terminal (9).

摘要翻译： 本发明提供了一种具有高可靠性的CSP型半导体器件。 半导体器件包括形成在半导体衬底（1）上的绝缘膜（2,3）的焊盘电极（4），形成在焊盘电极（4）上的镀层（7），导电端子（9） 形成在所述镀层上并与所述焊盘电极（4）电连接;以及覆盖所述绝缘膜（2,3）的第一钝化膜（5）和所述焊盘电极（4）的侧端部， 通过形成第二钝化膜（10）覆盖引起腐蚀的焊盘电极（4）的一部分，以覆盖第一钝化膜（5），镀层（7）和导电的侧壁的一部分 终端（9）。

公开(公告)号：EP1777740A3

公开(公告)日：2009-04-01

申请号：EP06020446.8

申请日：2006-09-28

申请人： Sanyo Electric Co., Ltd.

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/31 ,  H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/562 ,  H01L23/564 ,  H01L2221/6834 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16237 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/00014

摘要： The invention prevents a pad electrode (3) for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode (3) connected to the electronic circuit, and a second pad electrode (4) connected to the first pad electrode (3) are formed on a semiconductor substrate (1). A first protection film (5) is formed, covering the first pad electrode (3) and having an opening on the second pad electrode (4) only. A wiring layer (10) is further formed, being connected to the back surface of the first pad electrode (3) through a via hole penetrating the semiconductor substrate (1) and extending from the via hole onto the back surface of the semiconductor substrate (1).

公开(公告)号：EP1734579A2

公开(公告)日：2006-12-20

申请号：EP06012323.9

申请日：2006-06-14

申请人： Sanyo Electric Co., Ltd

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/485

CPC分类号： H01L23/3192 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode (4) formed on a semiconductor substrate (1), a first passivation film (5) covering an end portion of the pad electrode (4) and having a first opening (6) on the pad electrode (4), a plating layer (7) formed on the pad electrode (4) in the first opening (6), a second passivation film (9) covering an exposed portion of the pad electrode (4) between an end portion of the first passivation film (5) and the plating layer (7), covering an end portion of the plating layer (7), and having a second opening (10) on the plating layer (7), and a conductive terminal (11) formed on the plating layer (7) in the second opening (10).

摘要翻译： 本发明提供了一种高可靠性的CSP型半导体器件。 该半导体器件包括形成在半导体衬底（1）上的焊盘电极（4），覆盖焊盘电极（4）的端部且在焊盘电极上具有第一开口（6）的第一钝化膜（5） 在所述第一开口部的所述焊盘电极上形成的电镀层;覆盖所述焊盘电极的露出部分的第二钝化膜， 覆盖镀层（7）的端部并且在镀层（7）上具有第二开口（10）的钝化膜（5）和镀层（7），以及形成在其上的导电端子（11） 在第二开口（10）中的镀层（7）。