公开(公告)号：EP3363048A1

公开(公告)日：2018-08-22

申请号：EP16785621.0

申请日：2016-10-06

申请人： Xilinx, Inc.

发明人： CHAWARE, Raghunandan ,  MAJUMDAR, Amitava ,  O'ROURKE, Glenn ,  SINGH, Inderjit

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

摘要： Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：EP3257078A1

公开(公告)日：2017-12-20

申请号：EP16704113.6

申请日：2016-01-26

申请人： Qualcomm Incorporated

发明人： SYED, Ahmer, Raza ,  KIM, Chin-Kwan ,  BCHIR, Omar, James ,  SHAH, Milind, Pravin ,  LANE, Ryan, David

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L23/13 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/32 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/15158 ,  H01L2924/15333

摘要： A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.

公开(公告)号：EP1675171A3

公开(公告)日：2007-10-31

申请号：EP05027762.3

申请日：2005-12-19

申请人： Seiko Epson Corporation

发明人： Ito, Haruki

IPC分类号： H01L23/31 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： A semiconductor device (1) includes: a semiconductor substrate (10) having an active surface (10A) and a back surface (10B); an integrated circuit formed on the active surface (10A); a feedthrough electrode (12) penetrating the semiconductor substrate (10), and projecting from the active surface (10A) and the back surface (10B); a first resin layer (18) formed on the active surface (10A), having a thickness greater than a height of a portion of the feedthrough electrode (12) that projects from the active surface (10A), and having an opening portion (18H) for exposing at least a portion of the feedthrough electrode (12); a wiring layer (21) which is formed on the first resin layer (18), and which is connected to the feedthrough electrode (12) through the opening portion (18H); and an external connecting terminal (23) connected to the wiring layer (21).

公开(公告)号：EP1675171B1

公开(公告)日：2014-04-09

申请号：EP05027762.3

申请日：2005-12-19

申请人： Seiko Epson Corporation

发明人： Ito, Haruki

IPC分类号： H01L23/31 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

公开(公告)号：EP2406816A4

公开(公告)日：2013-04-03

申请号：EP10751155

申请日：2010-02-10

申请人： MICRON TECHNOLOGY INC

发明人： LI JIN ,  JIANG TONGBI

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/76898 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/27416 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/013

公开(公告)号：EP1505643B1

公开(公告)日：2012-11-14

申请号：EP04018715.5

申请日：2004-08-06

申请人： SANYO ELECTRIC CO., LTD.

发明人： Noma, Takashi ,  Kitagawa, Katsuhiko ,  Otsuka, Hisao ,  Suzuki, Akira ,  Seki, Yoshinori ,  Takao,Yukihiro ,  Yamaguchi, Keiichi ,  Wakui, Motoaki ,  Iida, Masanori

IPC分类号： H01L23/31 ,  H01L21/68

CPC分类号： H01L24/13 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

公开(公告)号：EP2406816A1

公开(公告)日：2012-01-18

申请号：EP10751155.2

申请日：2010-02-10

申请人： Micron Technology, Inc.

发明人： LI, Jin ,  JIANG, Tongbi

IPC分类号： H01L21/60 ,  H01L21/02 ,  H01L21/68 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/27416 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for fabricating semiconductor components (90) includes the steps of: providing a semiconductor substrate (52) having a circuit side (54), a back side (56) and conductive vias (58); removing portions of the substrate (52) from the back side (56) to expose terminal portions (76) of the conductive vias (58); depositing a polymer layer (78) on the back side (56) encapsulating the terminal portions (76); and then planarizing the polymer layer (78) and ends of the terminal portions (76) to form self aligned conductors embedded in the polymer layer (78). Additional back side elements, such as terminal contacts (86) and back side redistribution conductors (88), can also be formed in electrical contact with the conductive vias (58). A semiconductor component (90) includes the semiconductor substrate (52), the conductive vias (58), and the back side conductors embedded in the polymer layer (78). A stacked semiconductor component (96) includes a plurality of components (90-1, 90-2, 90-3) having aligned conductive vias (58) in electrical communication with one another.

公开(公告)号：EP1668745B1

公开(公告)日：2011-08-31

申请号：EP03770552.2

申请日：2003-09-30

申请人： International Business Machines Corporation

发明人： VOLANT, Richard, P. ,  PETRARCA, Kevin, S. ,  WALKER, George, F.

IPC分类号： H01R12/00

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

摘要翻译： 描述了由多个折叠的集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片电连接的互连路径，并且至少一个芯片（130）是 具有附加到衬底（500），封装或印刷电路板的互连布线。 进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

公开(公告)号：EP1668745A1

公开(公告)日：2006-06-14

申请号：EP03770552.2

申请日：2003-09-30

申请人： International Business Machines Corporation

发明人： VOLANT, Richard, P. ,  PETRARCA, Kevin, S. ,  WALKER, George, F.

IPC分类号： H01R12/00

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

公开(公告)号：EP3155654A1

公开(公告)日：2017-04-19

申请号：EP14895326.8

申请日：2014-06-16

申请人： Intel Corporation ,  Nelson, Don W. ,  Webb, Milton Clair ,  Morrow, Patrick ,  Jun, Kimin

发明人： NELSON, Donald W. ,  WEBB, M. Clair ,  MORROW, Patrick ,  JUN, Kimin

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L25/0652 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/8221 ,  H01L23/427 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/0922 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/00

摘要： A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

摘要翻译： 一种方法，包括在衬底上形成多个第一器件和多个第一互连件; 将包括多个第二设备的第二设备层耦合到所述多个第一互连中的一个，并且在所述第二设备层上形成多个第二互连。 一种包括第一装置层的装置，包括设置在多个第一互连和多个第二互连之间的多个第一电路装置和第二装置层，所述第二装置层包括并置并耦合到所述多个第一互连中的一个的多个第二装置， 所述多个第二互连，其中所述多个第一装置和所述多个第二装置中的一个包括具有比所述多个第一装置和所述多个第二装置中的另一个更高的电压范围的装置。