公开(公告)号：EP0729019A3

公开(公告)日：1996-12-11

申请号：EP96102659.8

申请日：1996-02-22

申请人： MOTOROLA, INC.

发明人： Meyer, Brian D. ,  Baskett, Ira E.

IPC分类号： G01L9/06

CPC分类号： G01L9/0054 ,  Y10T29/49101 ,  Y10T29/49103

摘要： A piezoresistive pressure sensor (30) has four resistive diffused regions (32) coupled into a bridge configuration (33) with four junctions (36). Each of the diffused regions has a first end connected to one of the four junctions and a second end connected to a different one of the four junctions. There are four contact diffusion terminals (34) disposed in contact with the bridge configuration, and each of the diffusion terminals is disposed at one of the four junctions such that the diffused regions are electrically connected essentially only by the contact diffusion terminals. Thus, no tap is required to electrically connect the contact diffusion terminals to the resistive diffused regions of the bridge, which results in increased sensor sensitivity.

公开(公告)号：EP0746022A1

公开(公告)日：1996-12-04

申请号：EP96108455.5

申请日：1996-05-28

申请人： MOTOROLA, INC.

发明人： Scanlan, Christopher M. ,  Raleigh, Carl J.

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/3735 ,  H01L23/367 ,  H01L23/3731 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A hybrid multi-chip module includes semiconductor chips (27,31) bonded to a base plate (24). The base plate includes a substrate (11) having two surfaces (12,13) and a conductive material (32) molded on the two surfaces (12,13). A coefficient of thermal expansion (CTE) mismatch between the substrate (11) and the conductive material (32) at the first surface (12) is balanced by a similar, but opposite, CTE mismatch between the substrate (11) and the conductive material (32) at the second surface (13). The CTE mismatch balance across the base plate (24) produces a base plate (24) having a substantially planar form at high temperatures.

摘要翻译： 混合多芯片模块包括结合到基板（24）的半导体芯片（27,31）。 基板包括具有两个表面（12,13）和模制在两个表面（12,13）上的导电材料（32））的基板（11）。 在第一表面（12）处的衬底（11）和导电材料（32）之间的热膨胀系数（CTE）不匹配由衬底（11）和导电材料之间的相似但相反的CTE失配来平衡 （32）在第二表面（13）处。 基板（24）上的CTE失配平衡产生在高温下具有基本上平面形状的基板（24）。

公开(公告)号：EP0744691A2

公开(公告)日：1996-11-27

申请号：EP96107081.0

申请日：1996-05-06

申请人： MOTOROLA, INC.

发明人： Chu, Michael C.K. ,  Yiu, Hing Leung

IPC分类号： G06F9/46

CPC分类号： G06F9/5011 ,  G06F9/5094 ,  Y02D10/22

摘要： In a portable electronic device, a method and apparatus for providing a predetermined portion of a limited resource from a programmable resource allocators (PRAs) 240 to a processor 22 to execute a task 210 optimally. The processor 22 programming the PRA with a resource utilization input (RUI) 250 prior to executing the task 210. The RUI 250 stored in a task descriptor 220, and the task descriptor 220 and the task 210 stored in the memory 200.

摘要翻译： OPTI马利在便携式电子设备中，用于提供有限的资源的预定部分从一个可编程资源分配器（的PRA）240到处理器22的方法和装置来执行任务第二百十 处理器22与资源利用率输入（RUI）编程的PRA 250之前执行任务210存储在任务描述符220中的RUI 250和任务描述符220和存储在存储器200中任务210以

公开(公告)号：EP0598006B1

公开(公告)日：1996-11-20

申请号：EP92917243.5

申请日：1992-08-03

申请人： MOTOROLA, INC.

发明人： MOORE, Kevin, D. ,  STAFFORD, John, W. ,  BECKENBAUGH, William, M. ,  CHOLEWCZYNSKI, Kenneth

IPC分类号： B23K31/02 ,  B44C1/22 ,  H05K3/00 ,  B23K1/00 ,  H01L21/48

CPC分类号： H05K3/3457 ,  B23K1/0016 ,  H01L2224/814 ,  H05K1/11 ,  H05K1/111 ,  H05K3/062 ,  H05K3/3473 ,  H05K2201/09381 ,  H05K2203/042 ,  H05K2203/043 ,  H05K2203/0723 ,  Y02P70/611 ,  H01L2924/014

摘要： A solder bump (30, 124) is formed on a circuit trace by a method that includes depositing onto the trace a uniform thin plate (26, 124) of solder alloy and reflowing the solder alloy to form the bump. In one aspect of this invention, the trace comprises first and second linear sections (18, 20) that intersect at an intersection (22) whereat the bump is formed. In another aspect of this invention, the trace includes a terminal (116) having an enlarged terminal pad (118) connected to a runner section (120), whereupon the bump forms at the pad. The solder plate is deposited, preferably by electroplating, at a thickness between about 10 and 25 microns. Thereafter, when the trace is heated to melt the solder layer, the solder coalesces to form the bump having a height preferably greater than 40 microns.

摘要翻译： 通过包括在迹线上沉积焊料合金的均匀薄板（26,124）并回流焊料合金以形成凸块的方法在电路迹线上形成焊料凸点（30,124）。 在本发明的一个方面，迹线包括第一和第二线性部分（18,20），它们在形成凸块的交点（22）处相交。 在本发明的另一方面，迹线包括具有连接到流道部分（120）的扩大的端子垫（118）的端子（116），于是凸块在垫上形成。 优选通过电镀以大约10至25微米的厚度沉积焊盘。 之后，当迹线被加热以熔化焊料层时，焊料聚结以形成高度优选大于40微米的凸块。

公开(公告)号：EP0741453A2

公开(公告)日：1996-11-06

申请号：EP96106750.1

申请日：1996-04-29

申请人： MOTOROLA, INC.

发明人： Rybicki, Mathew A. ,  Cave, Michael D.

IPC分类号： H03K3/03

CPC分类号： H03K3/012 ,  H03K3/03

摘要： The output frequency (14) of an oscillator circuit (10) can be controlled by replacing at least one of the reactive components (40), such as a capacitor or inductor, with a synthesized element (22). The synthesized element creates a signal that corresponds to the response of the reactive component it is replacing. The synthesized element may be a current source (44), such as a field effect transistor, that is capable of operating at low voltages.

摘要翻译： 诸如电容器或电感器，具有合成元件（22）：振荡电路（10）的输出频率（14）可以通过更换反应性组分（40）中的至少一个进行控制。 合成的元件创建的信号做了对应于所要替换的无功分量的响应。 合成元件可以是电流源（44）：如场效应晶体管，确实能够在低电压下工作的。

公开(公告)号：EP0741417A2

公开(公告)日：1996-11-06

申请号：EP96106751.9

申请日：1996-04-29

申请人： MOTOROLA, INC.

发明人： Abrokwah, Jonathan K. ,  Huang, Jenn-Hwa ,  Ooms, William J. ,  Shurboff, Carl L. ,  Hallmark, Jerald A.

IPC分类号： H01L29/778 ,  H01L29/45 ,  H01L27/085 ,  H01L21/335

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L27/085 ,  H01L29/0891 ,  H01L29/41766 ,  H01L29/452

摘要： A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

公开(公告)号：EP0741388A2

公开(公告)日：1996-11-06

申请号：EP96106735.2

申请日：1996-04-29

申请人： MOTOROLA, INC.

发明人： Tai, Jy-Der David

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferro-electric memory array (41) having a reduced size and increased performance is disclosed herein. The ferro-electric memory array (41) is arrayed in memory cell columns and memory cell rows. Each memory cell column shares a BIT or BITBAR line with an adjacent memory cell column. Two row enable lines are provided to each memory cell row. The row enable lines alternately couple to memory cells of a memory cell row to prevent a contention condition. Sharing BIT and BITBAR lines with adjacent memory cell columns reduces a width of the ferro-electric memory array (41) which reduces the resistance on each line CP for a memory cell row. The result is a memory array that is capable of operating at higher speeds. Also, using more than one row enable line in each row reduces the number of memory cells accessed in a read or write operation. This increases the endurance of the ferro-electric memory array (41) by a factor of two.

公开(公告)号：EP0681186A3

公开(公告)日：1996-11-06

申请号：EP95105785.0

申请日：1995-04-18

申请人： MOTOROLA, INC.

发明人： Lum, Thomas F. ,  Wenzel, James F.

IPC分类号： G01R1/073

CPC分类号： G01R1/07378 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311

摘要： A method for probing a semiconductor wafer utilizes an array probe assembly (60) which includes a production package substrate (64). Substrate (64) is used to transform a configuration of conductive pads (74) on a probe card (62) into a configuration which matches that of conductive bumps (54) on a semiconductor die (52). Array probe assembly (60) may also include an array probe head (68) having probe wires (84) for coupling conductive pads (80) on substrate (64) with conductive bumps (54) on die (52). After probing the die, the die are assembled into a final packaged semiconductor device (110) which includes a substrate (90) which is nearly identical to the substrate used in the array probe assembly. Use of a prodution package substrate in the array probe assembly reduces the cost of the array probe assembly, and results in more accurate testing since the substrate in the array probe assembly will emulate the performance of the die in the final packaged device.

公开(公告)号：EP0624946A3

公开(公告)日：1996-10-16

申请号：EP94303240.9

申请日：1994-05-05

申请人： MOTOROLA, INC.

发明人： Williams, Gregory L. ,  Roman, William C.

IPC分类号： H02P7/67

CPC分类号： H02P5/00

摘要： A cellular motor control network (20) including a service center (22) and a plurality of local cell controllers (24,25,26) in communication with the service center, with each of the plurality of local cell controllers (24,25,26) having a plurality of cellular motor controls (30) in communication therewith. Each cellular motor control (30) coupled to a variable speed electric motor (72). The cellular motor control (30) including control circuits (76,77,78,80,82,87,88) for controlling the operation of the variable speed electric motor, a microprocessor (85) coupled to the control circuits for providing a predetermined control program, and a transceiver (90) coupled to the microprocessor for communicating information between the microprocessor and other control units in the network.

公开(公告)号：EP0736897A2

公开(公告)日：1996-10-09

申请号：EP96104675.2

申请日：1996-03-25

申请人： MOTOROLA, INC.

发明人： Perera, Asanga H.

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.

摘要翻译： 用沟槽隔离制造的集成电路的可靠性是通过用无空隙的沟槽插塞（36）形成沟槽隔离结构的改善。 在一个，实施例的多晶硅层（28）的沟槽（22）内形成，随后氧化，以形成一第一介电层（30）。 第一电介质层（30）随后被蚀刻和第二介电层（34）被蚀刻的介电层（32）在随后形成的。 第二电介质层（34）的一部分，然后使用化学机械抛光，以形成沟槽（22）内的无空隙的沟槽插塞（36）中除去。 此外，可靠性因此由它已经形成之后最小化沟槽插塞（36）的随后的蚀刻改善。