公开(公告)号：EP2056351B1

公开(公告)日：2018-09-26

申请号：EP08253585.7

申请日：2008-10-31

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01L29/778 ,  H01L29/812 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417

CPC分类号： H01L29/7787 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/812 ,  H01L29/8124

摘要： A semiconductor device includes: a substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width W A1 of the active area between gate and source is wider than width W A2 of the active area between gate and drain. Channel resistance of an active area between source and gate placed between a gate electrode and a source electrode is reduced, and high-frequency performance is provided.

公开(公告)号：EP1929538A2

公开(公告)日：2008-06-11

申请号：EP06793618.7

申请日：2006-09-19

申请人： SiCED Electronics Development GmbH & Co KG

发明人： MITLEHNER, Heinz ,  STEPHANI, Dietrich

IPC分类号： H01L29/872 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/0847 ,  H01L29/0891 ,  H01L29/1608 ,  H01L29/8611 ,  H01L29/872

摘要： The invention relates to a vertical integrated JBS-SiC semiconductor component, in particular to a power semiconductor component, comprising a high-doped SiC semiconductor body of a first conductivity type, a low-doped drift area of the first conductivity type, which is located on said semiconductor body on a transmitter side and which is at least partially adjacent to a first surface, at least one emitter area of a second conductivity type, which is integrated into the drift area on the first surface side and is adjacent thereto, an intermediate layer of the first conductivity type which is arranged in the drift area, at a distance from the emitter areas, laterally crosses the entire drift area and whose dopant concentration is greater than that of the drift area.

摘要翻译： 垂直集成JBS-SiC半导体器件技术领域本发明涉及一种垂直集成JBS-SiC半导体器件，尤其涉及一种功率半导体器件，其包括第一导电类型的高掺杂SiC半导体本体，第一导电类型的低掺杂漂移区域 在发射器侧的所述半导体本体上并且其至少部分地与第一表面相邻;第二导电类型的至少一个发射极区域，所述第二导电类型的发射极区域被集成到所述第一表面侧上的所述漂移区域中并且与所述第一表面侧壁相邻; 所述第一导电类型的层与所述发射极区域相距一定距离地布置在所述漂移区域中，横向穿过整个漂移区域，并且其掺杂剂浓度大于所述漂移区域的掺杂浓度。

公开(公告)号：EP0514079B1

公开(公告)日：1998-07-15

申请号：EP92304094.3

申请日：1992-05-07

申请人： RAYTHEON COMPANY

发明人： Huang, John C. ,  Jackson, Gordon S.

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/0891 ,  H01L29/7783

公开(公告)号：EP0680076A3

公开(公告)日：1997-01-15

申请号：EP95105788.4

申请日：1995-04-18

申请人： MOTOROLA, INC.

发明人： Davies, Robert B. ,  Anderson, Charles B. ,  Klingbeil, Lawrence S., Jr. ,  Norris, George B.

IPC分类号： H01L21/28 ,  H01L21/338

CPC分类号： H01L29/66878 ,  H01L21/266 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/812 ,  Y10S438/965

摘要： A semiconductor device having a short gate length is fabricated. The short gate length is obtained by utilizing the fact that an unannealed silicon nitride (17) can be isotropically etched while not etching an annealed silicon nitride layer (13).

公开(公告)号：EP0680092A2

公开(公告)日：1995-11-02

申请号：EP95105789.2

申请日：1995-04-18

申请人： MOTOROLA, INC.

发明人： Gilbert, James G. ,  Klingbeil, Lawrence S., Jr. ,  Halchin, David J. ,  Golio, John M.

IPC分类号： H01L29/10 ,  H01L21/338

CPC分类号： H01L29/66878 ,  H01L29/0891 ,  H01L29/1029 ,  H01L29/812

摘要： A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

摘要翻译： 一种场效应晶体管（10）具有在衬底（12）形成的活性层（16）上。 栅极（20），在从所述活性层（16）而形成高架平台（18）被布置在。 升高的平台（18）提高了栅极（20）相对于所述有源区域（13）的顶表面（34，36）上的栅极（20）的任一侧的底表面（21）。 用于晶体管（10）的制造方法形成所述高架平台（18）通过在所述栅极（20）象栅极的底表面（21）（20）的bothsides蚀刻有源区表面（44）是升高的 相对于周围的有源区域（13）的顶面（34）。 栅极（20）本身和/或图案化的光刻胶层（116）可以被用作用于执行该蚀刻的掩模。

公开(公告)号：EP0665596A1

公开(公告)日：1995-08-02

申请号：EP94119677.6

申请日：1994-12-13

申请人： FUJITSU LIMITED

发明人： Wada, Jun, c/o Fujitsu Quantum Devices Limited

IPC分类号： H01L29/10 ,  H01L29/772 ,  H01L21/338

CPC分类号： H01L29/66878 ,  H01L29/0891 ,  H01L29/1075

摘要： In a MESFET of this invention possessed of an LDD structure, a current control layer (11) possessed of conduction type opposite to that of an active layer (12) is formed below the active layer (12). In the part of this current control layer (11) underlying a gate electrode (13), a low impurity concentration region (12c) destined to function as a channel region for a transistor is formed. Further, LDD regions (12b) are formed at both sides of the channel region (12c). In the current control layer (11), the part (11a) underlying the channel region (12c) is kept at a low impurity concentration while the other parts (11b) underlying the LDD regions (12b) are kept at a higher impurity concentration than the part (11a) underlying the channel region. Thus, a MESFET possessed of an improved short channel effect and excellent high frequency characteristics is obtained.

摘要翻译： 在具有LDD结构的本发明的MESFET中，在有源层（12）的下方形成具有与有源层（12）相反的导电类型的电流控制层（11）。 在栅极（13）下面的该电流控制层（11）的部分中，形成旨在用作晶体管的沟道区的低杂质浓度区域（12c）。 此外，LDD区域（12b）形成在沟道区域（12c）的两侧。 在电流控制层（11）中，沟道区（12c）下面的部分（11a）保持在低杂质浓度，而LDD区（12b）下面的其它部分（11b）保持在比 位于通道区域下方的部分（11a）。 因此，具有改善的短沟道效应的MESFET获得了优异的高频特性。

公开(公告)号：EP0613190A3

公开(公告)日：1995-04-12

申请号：EP94102643.7

申请日：1994-02-22

申请人： Sumitomo Electric Industries, Ltd.

发明人： Nakajima, Shigeru, c/o Yokohama Works of

IPC分类号： H01L29/812 ,  H01L29/08 ,  H01L21/338

CPC分类号： H01L29/0891

摘要： This invention has as its object to easily obtain a MESFET free from output distortion. For this purpose, in this invention, an n⁺-type layer (4) is formed at a substrate position spaced apart from a gate electrode (7) by a distance of a side-etch amount L g-n+ . The n⁺-type layer (4) has an impurity concentration and thickness such that a surface depletion layer generated depending on a surface level on the drain-side does not almost extend to the drain-side. An n'-type layer (5) as an intermediate concentration layer has an impurity concentration and thickness such that a drain-side end portion of a channel depletion layer generated upon applying a voltage to the gate electrode (7) extends to the drain-side with an increase in this applied voltage. Moreover, the n⁺-type layer (4), a distance L g-n+ , and the n'-type layer (5) are formed to have a relationship in which a ratio of an extension length L of the drain-side end portion of the channel depletion layer from the drain-side end portion A of the gate electrode (7) to the drain-side, to a gate length L g falls within a predetermined range. Therefore, according to this invention, the long gate effect and the effect for the drain current in accordance with the square characteristics cancel each other, and an FET output changes linearly in response to an input.

摘要翻译： 本发明的目的是容易地获得没有输出失真的MESFET。 为此，在本发明中，在与栅电极（7）隔开距离侧蚀刻量Lg-n +的基板位置处形成n +型层（4）。 n +型层（4）具有杂质浓度和厚度，使得根据漏极侧的表面电平而产生的表面耗尽层几乎不延伸到漏极侧。 作为中间浓度层的n型层（5）具有杂质浓度和厚度，使得在向栅电极（7）施加电压时产生的沟道耗尽层的漏极侧端部延伸到漏极 - 这个施加电压增加。 此外，n +型层（4），距离Lg-n +和n'型层（5）形成为具有这样的关系，其中漏极侧的延伸长度L 从栅电极（7）的漏极侧端部A到漏极侧的沟道耗尽层的端部到栅极长度Lg落在预定范围内。 因此，根据本发明，长栅效应和根据平方特性的漏极电流的影响相互抵消，并且FET输出响应于输入而线性变化。

公开(公告)号：EP0598711A3

公开(公告)日：1994-08-24

申请号：EP94200376.5

申请日：1989-11-29

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Oku, Tomoki, c/o Mitsubishi Denki Kabushiki Kaisha

IPC分类号： H01L29/812 ,  H01L29/08

CPC分类号： H01L29/66878 ,  H01L29/0891

摘要： A transistor (fig. 1(i)) having a refractory metal gate (3) on a semi-insulating compound semiconductor substrate (1), asymmetrical side walls (5',7') each side of the gate (3), a low concentration active channel (2) below the gate (3),
   source and drain high concentration active regions (8a,8b) each side of the channel (2), and asymmetric intermediate concentration active regions (4a',4b') between source (8a) and channel (2), and channel (2) and drain (8b), respectively, beneath the asymmetrical side walls (5',7'). The side walls (5',7') may be removed.

摘要翻译： 构成肖特基势垒栅型场效应晶体管的半导体器件的制造方法包括以下步骤：在半绝缘化合物半导体衬底的期望位置处产生低浓度有源区，并在有源区上产生包含难熔金属的栅电极 制造第一绝缘膜并对其进行蚀刻，从而在栅电极的两侧壁产生包括第一绝缘膜的第一侧壁辅助膜，在源电极的一侧除去第一侧壁辅助膜之一 通过湿蚀刻制造，将第二绝缘膜电镀至比第一绝缘膜小的厚度，蚀刻第二绝缘膜，从而制造宽度比第一侧壁辅助膜宽的第二侧壁辅助膜 在栅极电极的制造源电极侧的侧壁上进行导通 使用第一和第二侧壁辅助膜和栅极电极作为掩模的离子注入，从而在栅电极的两侧的左右处产生不对称构造的高浓度有源区。

公开(公告)号：EP0565054A3

公开(公告)日：1994-07-27

申请号：EP93105687.3

申请日：1993-04-06

申请人： Hughes Aircraft Company

发明人： Hasenberg, Thomas C. ,  Brown, April S. ,  Larson, Lawrence E.

IPC分类号： H01L29/201 ,  H01L29/207 ,  H01L21/38 ,  H01L29/76 ,  H01L29/14 ,  H01L29/205

CPC分类号： H01L29/0847 ,  H01L21/28575 ,  H01L29/0891 ,  H01L29/155 ,  H01L29/66462 ,  H01L29/7783 ,  Y10S148/16 ,  Y10S438/938

摘要： High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al x Ga 1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al y Ga 1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.

摘要翻译： 通过在III-Sb基层上形成具有III-V族化合物的n掺杂应变层的超晶格，在分子束外延工艺中n掺杂高速III-Sb族材料。 基层具有比应变层更低的导带能级，并允许从应变层掺杂电子流入基层。 基层优选包含Al x Ga 1-x Sb，而应变层优选包含二元或三元化合物，例如具有单一V族组分的AlyGa1-yAs，其中x和y各自为0至1.0。 应变层可以用硅或锡进行n掺杂，如果直接添加到基层，则会产生p型掺杂。

公开(公告)号：EP0574827A1

公开(公告)日：1993-12-22

申请号：EP93109321.5

申请日：1993-06-10

申请人： SANYO ELECTRIC CO., LIMITED.

发明人： Harada, Yasoo ,  Matsushita, Shigeharu ,  Terada, Satoshi ,  Fujii, Emi ,  Kurose, Takashi ,  Higashino, Takayoshi ,  Yamada, Takashi ,  Nagamatsu, Akihito ,  Inoue, Daijirou ,  Matsumura, Kouji

IPC分类号： H01L21/225 ,  H01L21/335

CPC分类号： B82Y10/00 ,  H01L21/22 ,  H01L21/2258 ,  H01L21/28587 ,  H01L21/28593 ,  H01L21/3144 ,  H01L21/3245 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/1025 ,  H01L29/66075 ,  H01L29/66196 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66856 ,  H01L29/66871 ,  H01L29/66878 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8605 ,  Y10S148/034 ,  Y10S438/962

摘要： A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.

摘要翻译： 掺杂有III-V族化合物半导体的杂质的方法，其中在未掺杂的SiOx膜和用于防止V族原子扩散的膜（例如，SiN膜）之后依次形成组的晶体 III-V族化合物半导体，对该样品进行至少一次热处理以使SiOx膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。 使用这种掺杂层形成方法，制造场效应晶体管，二极管，电阻层，二维电子气或一维量子线，零维量子箱，电子波干涉装置等。