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    SDRAM ADDRESS MAPPING OPTIMIZED FOR TWO-DIMENSIONAL ACCESS
    14.
    发明授权
    SDRAM ADDRESS MAPPING OPTIMIZED FOR TWO-DIMENSIONAL ACCESS 有权
    SDRAM地址PICTURE增强了对二维触摸

    公开(公告)号：EP1568036B1

    公开(公告)日：2008-08-27

    申请号：EP03772445.7

    申请日：2003-11-14

    申请人： NXP B.V.

    发明人： VAN DE WAERDT, Jan-Willem, Philips Elec. N.A. Corp

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1042 ,  G06F12/0207 ,  G11C11/4087

    摘要： Typically, a bulk of the memory space utilized by an SOC (103) is located in cheaper off-chip memory devices such as Synchronous Dynamic Random Access Memory (SDRAM) memories (104). These memories provide a large capacity for data storage, at a relatively low cost. It is common for SOC devices to communicate with each other through these off-chip memory devices. Because of the large amount of data being processed on state of the art SOCs, the data bandwidth to and from the SDRAM memories is a critical resource, which if improperly managed results in bottlenecks. Thus, a novel address mapping scheme, which has improved efficiency for two-dimensional memory transactions is proposed for mapping on-chip memory transactions to off-chip memory transactions. This novel mapping scheme aims to decrease these bottlenecks, by segmenting the data sequence into portions being smaller than the size of a row of a block of the SDRAM memories.

    Memory device, memory controller and memory system
    15.
    发明公开
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：EP1936631A1

    公开(公告)日：2008-06-25

    申请号：EP07112350.9

    申请日：2007-07-12

    申请人： Fujitsu Ltd.

    发明人： Sato, Takahiko c/o FUJITSU LIMITED ,  Uchida, Toshiya c/o FUJITSU LIMITED ,  Kanda, Tatsuya c/o FUJITSU LIMITED ,  Miyamoto, Tetsuo c/o FUJITSU LIMITED ,  Shirakawa, Satoru c/o FUJITSU LIMITED ,  Yamamoto, Yoshinobu c/o FUJITSU LIMITED ,  Otsuka, Tatsushi c/o FUJITSU LIMITED ,  Kurita, Masanori c/o FUJITSU LIMITED ,  Kamata, Shinnosuke c/o FUJITSU LIMITED ,  Sato, Ayako c/o FUJITSU LIMITED ,  Takahashi, Hidenaga c/o FUJITSU LIMITED

    IPC分类号： G11C11/408

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供了能够有效访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 该存储装置具有：存储单元阵列，其具有多个存储单元区域，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储器单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储器单元区域在其中分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储器单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 根据输入地址以及响应于第一操作码的字节或比特的组合信息，在与第一存储单元相邻的第二存储单元区域中存储与输入地址对应的单位区域，然后，从多个 字节或位，将基于组合信息的多个字节或位的组合与多个输入/输出端子相关联。

    METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH
    17.
    发明公开
    METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH 有权
    方法和设备最大化DRAM内存带宽

    公开(公告)号：EP1485919A2

    公开(公告)日：2004-12-15

    申请号：EP03714158.7

    申请日：2003-03-13

    申请人： INTEL CORPORATION

    发明人： KURUPATI, Sreenath

    IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C11/408

    CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4093

    摘要： A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

    High-speed cycle clock-synchronous memory device
    20.
    发明公开
    High-speed cycle clock-synchronous memory device 有权
    US US US US US US US US US US US US US US US US US US US US

    公开(公告)号：EP1223583A2

    公开(公告)日：2002-07-17

    申请号：EP02007295.5

    申请日：1999-07-16

    申请人： Kabushiki Kaisha Toshiba

    发明人： Toda, Haruki ,  Tsuchida, Kenji ,  Kuyama, Hitoshi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C11/4087

    摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier (S/A) shared by and between cell arrays, and a cell array controller unit (CNTRLi), wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access (S), between the neighboring cell arrays (N), or between remote cell arrays (F). According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S ≧ N ≧ F.

    摘要翻译： 高速时钟同步存储装置具有由单元阵列之间和单元阵列之间共享的读出放大器（S / A）和单元阵列控制器单元（CNTRLi），其中与时钟同步的数据/命令的输入和输出， 访问命令同时提供所有地址数据位（行和列）。 通过确认在两个连续命令之间观察到的位的变化，关于配置接入地址的一些地址位，设备判断当前接入是否在与之前的接入（S）相同的小区阵列内，在相邻小区阵列（N ）或远程单元阵列（F）之间。 根据判断，应用适当的命令循环。 此时，命令循环满足关系：S> / = N> / = F.