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    PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS
    11.
    发明授权
    PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS 有权
    使用双端口单元的单端口存储器和具有相关有效数据位的单端口单元及相关方法

    公开(公告)号：EP3038109B1

    公开(公告)日：2018-04-11

    申请号：EP15187696.8

    申请日：2015-09-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Rawat, Harsh ,  JAIN, PIYUSH

    IPC: G11C8/16 ,  G11C7/10 ,  G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

    Abstract: A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    12.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    VORRICHTUNG MIT EINER INTEGRIERTEN HALBLEITERSCHALTUNG

    公开(公告)号：EP3032540A4

    公开(公告)日：2017-03-15

    申请号：EP13891121

    申请日：2013-08-06

    Applicant: RENESAS ELECTRONICS CORP

    Inventor： NII KOJI

    IPC: H01L27/11 ,  G11C8/16 ,  G11C11/412 ,  H01L27/02

    CPC classification number: H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

    Abstract translation: 在处理图像信息等的芯片中，多端口SRAM与诸如数字信号处理电路的逻辑电路混合在一起。 在这种情况下，例如，在使用3端口的情况下，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 然而，在这种配置中，显然存在一个问题，即当嵌入式SRAM的占用面积减小时，写入和读出端口的数量仅限于一个，并且与差分读出一样快的读出特性不能 预计在单端读出。 本申请的概述是三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如，N阱区域被布置在单元的中心，并且P阱区域 布置在其两侧。

    Write contention-free, noise-tolerant multiport bitcell
    16.
    发明公开
    Write contention-free, noise-tolerant multiport bitcell 审中-公开
    Schreibkonfliktfreie，rauschtolerante Multiport-Bit-Zelle

    公开(公告)号：EP2648187A2

    公开(公告)日：2013-10-09

    申请号：EP13161832.4

    申请日：2013-03-29

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Ashok, Ambica ,  Ramaraju, Ravindraraj ,  Russell, Andrew C

    IPC: G11C8/14 ,  G11C8/16

    CPC classification number: G11C8/16 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C11/419

    Abstract: A multi-port memory cell (112) of a multi-port memory array (104) includes a first inverter (206) that is disabled by a first subset (WWL0-3) of a plurality of write word lines and a second inverter (204), cross coupled with the first inverter (206), wherein the second inverter (204) is disabled by a second subset (WWL4-7) of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter (204). The second selection circuit has data inputs coupled to a second subset (WBL4-7) of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter (206).

    Abstract translation: 多端口存储器阵列（104）的多端口存储单元（112）包括由多个写字线的第一子集（WWL0-3）禁用的第一反相器（206）和第二反相器（ 204），与第一反相器（206）交叉耦合，其中第二反相器（204）被多个写字线的第二子集（WWL4-7）禁用。 第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器（204）的输入的输出。 第二选择电路具有耦合到多个写入位线的第二子集（WBL4-7）的数据输入，耦合到多个写入字线的第二子集的选择输入以及耦合到第一个 逆变器（206）。

    SRAM cell with improved read stability
    18.
    发明公开
    SRAM cell with improved read stability 有权
    SRAM单元具有改进的读取稳定性

    公开(公告)号：EP2482285A3

    公开(公告)日：2012-09-19

    申请号：EP12151635.5

    申请日：2012-01-18

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Ramaraju, Ravindraraj

    IPC: G11C8/16 ,  G11C11/412

    CPC classification number: G11C11/412 ,  G11C8/16

    Abstract: An SRAM bitcell architecture is described having a dedicated read port (N0/N1/N6, N3/N4/N7) with pull up transistors (N6, N7) that shares at least a first bit line pair (23, 24) and word line signal (25), thereby providing separate data access read paths to a 6T SRAM architecture such that the read port is connected to drive the cell read node without exposing the memory cell during read operations and to act as a write port during write operations.

    Abstract translation: 描述了具有带上拉晶体管（N6，N7）的专用读取端口（N0 / N1 / N6，N3 / N4 / N7）的SRAM位单元架构，所述上拉晶体管至少共享第一位线对（23,24） 信号（25），由此向6T SRAM体系结构提供单独的数据访问读取路径，使得读取端口被连接以驱动单元读取节点而在读取操作期间不暴露存储器单元并且在写入操作期间充当写入端口。

    Semiconductor memory having dual port cell supporting hidden refresh
    20.
    发明公开
    Semiconductor memory having dual port cell supporting hidden refresh 审中-公开
    半导体存储器与适合于透明复习两端口细胞

    公开(公告)号：EP2287849A2

    公开(公告)日：2011-02-23

    申请号：EP10178106.0

    申请日：2001-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Keeth, Brent ,  Dennison, Chuck

    IPC: G11C11/406 ,  G11C11/405 ,  G11C8/16 ,  G11C11/403

    CPC classification number: G11C11/403 ,  G11C11/406 ,  Y10S257/907

    Abstract: The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access 0 device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.

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