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21.发明公开
公开(公告)号：EP4276889A1
公开(公告)日：2023-11-15
申请号：EP23172009.5
申请日：2023-05-08
Applicant: STMicroelectronics S.r.l.
Inventor： GOTTARDI, Thomas , MODARELLI, Nicoletta , CATALANO, Guendalina
IPC: H01L21/60 , H01L23/492 , H01L23/495
Abstract: A semiconductor die (14) is attached on a die-attachment portion (12A) of a planar substrate (12) and a planar electrically conductive clip (16) in mounted onto the semiconductor die (14). The electrically conductive clip (16) has a distal portion (16A) extending away from the semiconductor die (14) with the semiconductor die (14) sandwiched between the substrate (12) and the at least one electrically conductive clip (16). The substrate (12) includes electrically conductive leads (12B) arranged facing the distal portion (16A) of the electrically conductive clip (16) with a gap (G) formed therebetween.
The gap (G) is filled with a mass of gap-filling material (20) transferred to the gap (G) via Laser Induced Forward Transfer, LIFT processing, the mass (20) sized and dimensioned to fill the gap (G).-
公开(公告)号：EP4270771A1
公开(公告)日：2023-11-01
申请号：EP23163350.4
申请日：2023-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： D'ANGELO, Giuseppe
Abstract: A method for controlling a BLDC motor (11), comprising controlling the rotational speed and/or position of said BLDC motor (11) on the basis of a position of the rotor (θ) of the motor, said position of the rotor (θ) being computed sensing the back electromotive force (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ), said BLDC motor (11) being driven with three driving phases (VP 1 , VP 2 , VP 3 ) supplied to three-phase driving terminals ((N 1 , N 2 , N 3 ) by a three-phase inverter (13), comprising three arms (BR 1 , BR 2 , BR 3 ) comprising each a high side and a low side switch (MH 1 , ML 1 ; MH 2 , ML 2 ; MH 3 , ML 3 ), operating with a sinusoidal commutation, wherein
said method comprises calculating a current position of the rotor (θ) on the basis of zero-crossing times (ZC 1 , ZC 2 , ZC3 3 ) of back electromotive forces (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ), by the following steps:
generating a PWM signal (PWM 1 , PWM 2 , PWM 3 ) comprising three PWM phases comprising each a pair of complementary signals (TH 1 , TL 1 ; TH 2 , TL 2 ; TH 3 , TL 3 ) with dead-time (DT) which duty cycle (DC) value depends on a current position of the rotor (θ),
driving said three-phase inverter (13) supplying each signal of said pair of complementary signals (TH 1 , TL 1 ; TH 2 , TL 2 ; TH 3 , TL 3 ) with dead-time (DT) to a respective high side and low side switch (MH 1 , ML 1 ; MH 2 , ML 2 ; MH 3 , ML 3 ),
sensing back-electromotive forces (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ) at said three-phase driving terminals ((N 1 , N 2 , N 3 ) of said motor (11) and performing (15 1 , 15 2 , 15 3 ) a zero-crossing time measurement on each of said back electromotive forces (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ) obtaining corresponding signals indicating zero-crossing times (ZC 1 , ZC 2 , ZC3 3 ) which are supplied to said operation of calculating a current position of the rotor (θ) on the basis of zero-crossing times (ZC 1 , ZC 2 , ZC3 3 ) of back electromotive forces (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ),
computing (122) triggers signals (TR 1 , TR 2 , TR 3 ), which activate said performing (15 1 , 15 2 , 15 3 ) said zero-crossing time (ZC 1 , ZC 2 , ZC3 3 ) measurement on each of said back electromotive forces (BEMF 1 , BEMF 2 , BEMF 3 ; BEMF' 1 , BEMF' 2 , BEMF' 3 ), identifying the occurrence of a time interval corresponding to the dead time (DT) in the respective PWM phase (PWM 1 , PWM 2 , PWM 3 ; TH 1 , TL 1 ; TH 2 , TL 2 ; TH 3 , TL 3 ), and performing said zero-crossing time (ZC 1 , ZC 2 , ZC3 3 ) measurement during the occurrence of said dead-time (DT).-
公开(公告)号：EP4262091A1
公开(公告)日：2023-10-18
申请号：EP23161535.2
申请日：2023-03-13
Applicant: STMicroelectronics S.r.l.
Inventor： FORTUNATO, Davide Nicolo , CALCAGNO, Antonino , VINCIGUERRA, Marco , SCUDERI, Angelo , COSENTINO, Gaetano
Abstract: A voltage-controlled oscillator, VCO in a PLL circuit is calibrated via a dichotomous search in a set of candidate frequency bands (0, 31) via a sequence of subsequent halving steps (that produce reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) of the set of candidate frequency bands (0, 31). The reduced subsets (0, 15; 7, 15; 11, 15; 13, 15; 12, 14; 12, 13) have respective upper bound values (max; 15, 15, 15, 15, 14, 13), lower bound values (min; 0, 7, 11, 13, 12, 12) as well as central values (center; 7, 11, 13, 14, 13, 12). The central value of the subset resulting from the halving step of index i in the sequence is a function of the average ((max + min/2)) of the upper bound value (max) and the lower bound (min) value of the subset resulting from the halving step of index i-1 in the sequence.
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公开(公告)号：EP4262085A1
公开(公告)日：2023-10-18
申请号：EP23164021.0
申请日：2023-03-24
Applicant: STMicroelectronics S.r.l.
Inventor： STILGENBAUER, Francesco , CACCIAGRANO, Paolo , GONANO, Giovanni
Abstract: A digital audio playback circuit comprises a noise shaping circuit configured to receive an input digital audio signal, and a digital to analog converter (DAC) configured to convert the input digital audio signal to a pre-amplified output analog audio signal according to a gain ramp defined by a gain control signal. A muting circuit is configured to compare input digital audio signal to a threshold and assert a mute control signal when the input digital audio signal is below the threshold. An analog gain control ramp circuit is configured to generate the gain control signal in response to the mute control signal to cause the gain ramp to ramp down. An amplifier is configured to amplify the pre-amplified output analog audio signal for playback by an audio playback device.
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25.发明公开
公开(公告)号：EP4261693A1
公开(公告)日：2023-10-18
申请号：EP23161676.4
申请日：2023-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： VENEROSO, Amedeo , CIMINO, Carlo
Abstract: A method of managing memory (1084) in an integrated circuit card (108) using a Java Card platform, said integrated circuit card (108) comprising a non-volatile memory portion (51) and a RAM memory portion (52), said method comprising a procedure for the allocation of one or more transient arrays in said RAM memory portion (52), said procedure comprising
creating in a non-volatile memory heap (51) one or more array pointers (RA1, RA2, RA3), corresponding to one or more transient arrays (RB1, RB2, RB3) to be allocated, each array pointer (RA1, RA2, RA3) comprising a transient array size (BS) and a transient array address (LA; IA),
wherein
said creating (205) operation comprises
creating one or more array pointers (RA) comprising as transient array address a logical address (LA; IA) of the area of the RAM memory portion in which the respective transient array (RB1, RB2, RB3) is to be allocated
said procedure (200) further comprising
assigning (210) then in said RAM memory (52) area memory only to transient arrays (RB1, RB2, RB3), corresponding to said respective one or more array pointers (RA), which comprise at least a value different from zero.-
Patent Agency Ranking
公开(公告)号：EP4258550A1
公开(公告)日：2023-10-11
申请号：EP23161658.2
申请日：2023-03-14
Applicant: STMicroelectronics S.r.l.
Abstract: A method, comprising: producing (12) a set of delayed replicas (REF_D) of a reference clock signal (REF), wherein delayed replicas in the set of delayed replicas (REF_D) have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas (REF_D) from an edge of a clock signal (CK) having a clock period; selecting (16) based on edge detecting signals in the set of edge detecting signals a delayed replica (REF_Dj) in the set of delayed replicas (REF_D) having a distance from the clock signal edge (CK) that is shorter than the distance from the clock signal edge (CK) of any other delayed replica in the set of delayed replicas (REF_D); performing a comparison (18) of the clock period of the clock signal (CK) and of the selected delayed replica, obtaining as a result of the comparison, an error signal (CK_C) indicative of a difference therebetween, and providing the error signal (CK_C) to user circuitry (U) configured to calibrate the clock signal (CK) based on the error signal (CK_C).
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公开(公告)号：EP4258544A1
公开(公告)日：2023-10-11
申请号：EP23166296.6
申请日：2023-04-03
Inventor： ELGANI, Alessia Maria , D'ADDATO, Matteo , PERILLI, Luca , FRANCHI SCARSELLI, Eleonora , GNUDI, Antonio , CANEGALLO, Roberto Antonio , RICOTTI, Giulio
IPC: H03D1/18
Abstract: An envelope detector (50) having an envelope extracting portion (51) and a temperature compensating portion (52). The envelope extracting portion (51) has a first extraction transistor (13) and a second extraction transistor (14) coupled at an intermediate node (17). The first extraction transistor (13) has a first current conduction terminal coupled to a first connection node (16); a second current conduction terminal coupled to the intermediate node (17); and a control terminal coupled to the signal input node (23) and to a biasing node (24). The second extraction transistor (14) has a first current conduction terminal coupled to the intermediate node (17); a second current conduction terminal coupled to a second connection node (19); and a control terminal coupled to the biasing node (24). The temperature compensating portion (52) has a first temperature compensating transistor (58) that is diode-connected and coupled between a compensation output node (65) and the second connection node (19). The second connection node (19) is coupled to the compensation output node (65) and the first connection node (16) is coupled to a detector output (21).
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28.发明公开
公开(公告)号：EP4258362A1
公开(公告)日：2023-10-11
申请号：EP23166943.3
申请日：2023-04-06
Applicant: STMicroelectronics S.r.l.
Inventor： AMARA, Sebastiano , MENTA, Fernando Giovanni , PISANO, Salvatore
IPC: H01L29/739 , H01L29/08 , H01L29/36 , H01L21/331 , H01L21/265 , H01L21/683 , H01L29/423
Abstract: For manufacturing a vertical-channel semiconductor device (50), starting from a work wafer (1, 6) having a first side (1A) and a second side (1B) opposite to the first side along a direction (Z), a first doped region (42, 64) is formed in the work wafer, from the second side of the work wafer. The work wafer has a first conductivity type (N) and a first doping level, the first doped region has the first conductivity type and a second doping level higher than the first doping level. A device active region (25, 62) having a channel region (76) extending in the direction is formed in the work wafer, on the first side of the work wafer. The first doped region and the device active region delimit, in the work wafer, a drift region (30, 66). The first doped region is formed before the device active region.
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公开(公告)号：EP4246179A1
公开(公告)日：2023-09-20
申请号：EP23158628.0
申请日：2023-02-24
Applicant: STMicroelectronics S.r.l.
Inventor： LEONE, Antonio Davide , POLETTO, Vanni
IPC: G01S7/524 , G01S15/10 , G01S15/931 , B06B1/02 , G01S7/52
Abstract: An ultrasound transmitter device for driving piezoelectric transducers,
comprising a central-tap transformer (11) and a piezoelectric transducer (12) coupled to the terminals of the secondary output winding of said central-tap transformer (11) from which it receives a controlled current (Ip),
said central-tap transformer (11) comprising a primary winding, which includes terminals (DRV1, DRV2) at the ends of said primary winding and a central terminal (DRVC), said central terminal (DRVC) being coupled to a constant d.c. voltage, in particular a battery voltage (VBAT), said end terminals (DRV1, DRV2) being coupled, through respective transistors (Q1, Q2), in particular MOSFETs, which operate in push-pull mode, to a ground voltage (GND), said transistors (Q1, Q2) operating in push-pull mode being driven into their own open and closed states by respective complementary pulse sequences (SP, SPn), wherein:
said transmitter device (20) comprises a digital-to-analog converter (21), which supplies an analog current (Idac) to a driving amplifier (22) configured for determining the flowing of a driving current (Iout) in said transistors (Q1, Q2) operating in push-pull mode,
said transistors (Q1, Q2) operating in push-pull mode are coupled to said ground terminal (GND) through a sense resistance (Rsense),
the output of said digital-to-analog converter (21) is coupled to an input terminal (NR) of the driving amplifier (22), which is also coupled to the ground terminal (GND) through a reference resistance (Rref) having a value proportional to, in particular a multiple or a divisor of, the value of the sense resistance (Rsense),
said sense resistance (Rsense) being coupled to the other input terminal of the driving amplifier (22).-
公开(公告)号：EP4243261A1
公开(公告)日：2023-09-13
申请号：EP23156010.3
申请日：2023-02-10
Applicant: STMicroelectronics S.r.l.
Inventor： MORETTI, Emanuele , FLORIANI, Ivan , ALTAMURA, Giulia
Abstract: A control module (120) for a switching buck-boost converter (1) including an inductor (12), a capacitor (C OUT ), a first top switch (2) and a second top switch (4), a first bottom switch (6) and a second bottom switch (8) and a diode (24) coupled to the second top switch (4). The control module (120) controls the switching buck-boost converter (1) so as to alternate: first time periods (T switching ), in which the second top switch (4) is open and cycles of charge (T ON ,T' ON ) and discharge (T OFF ,T' OFF ) of the inductor (12) are carried out, during which the inductor (12) is traversed by a current (I L ) that also passes through the diode (24) and charges the capacitor (C OUT ); and second time periods (T OV_MODE ), in which the first and second top switches (2, 4) are open and the first and second bottom switches (6, 8) are closed so that the current (I L ) in the inductor (12) recirculates, and the capacitor (C OUT ) is discharged by a current (I LOAD ) that flows in the load (15). The control module (12) includes a circuit (60) that compares the duration (T OV_MODE ) of each second time period with a limit duration (Tth_ov) and detects the occurrence of an overcurrent if the duration (T OV_MODE ) of the second time period is shorter than the limit duration (Tth_ov).
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