公开(公告)号：EP1692724A4

公开(公告)日：2007-11-21

申请号：EP03796818

申请日：2003-12-08

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L27/148 ,  H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.

公开(公告)号：EP1644988A4

公开(公告)日：2007-04-11

申请号：EP04777137

申请日：2004-06-25

Applicant: IBM

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that begins by patterning a rectangular loop of semiconductor material (16) having two longer fins (21) and two shorter sections (22). The longer fins (21) are perpendicular to the shorter sections (22). The process continues by patterning a rectangular gate conductor (20) over central sections of the two longer fins (21), wherein the gate conductor (20) is perpendicular to the two longer fins (21). Next, the invention dopes portions of the semiconductor material (11) not covered by the gate conductor (20) to form source and drain regions in portions of the fins (21) that extend beyond the gate (20). Following this, the invention forms insulating sidewalls (31) along the gate conductor (20). Then, the invention covers the gate conductor (20) and the semiconductor material (11) with a conductive contact material (30) and forms a contact mask (40) over a portion of the conductive contact material (30) that is above source and drain regions of a first fin (42) of the two longer fins (21). The invention follows this by selectively etching regions of the conductive contact material (30) and the semiconductor material (11) not protected by the contact mask. This leaves the conductive contact material (30) on source and drain regions of the first fin (42) and removes source and drain regions of a second fin (41) of the two longer fins (21). This process forms a unique FinFET that has a first fin (42) with a central channel region (55) and source and drain regions (56) adjacent the channel region (55), a gate (20) intersecting the first fin (42) and covering the channel region (55), and a second fin (41) having only a channel region. The second fin is parallel to the first fin (42) and covered by the gate.

公开(公告)号：EP2070110A4

公开(公告)日：2012-01-25

申请号：EP07842398

申请日：2007-09-13

Applicant: IBM

Inventor： ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66613 ,  H01L29/66795 ,  H01L2029/7858

公开(公告)号：EP1920467A4

公开(公告)日：2011-03-02

申请号：EP06788172

申请日：2006-07-21

Applicant: IBM

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L29/06 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7856

公开(公告)号：EP1935020A4

公开(公告)日：2009-08-12

申请号：EP06825028

申请日：2006-09-19

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/84 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

公开(公告)号：EP1671376A4

公开(公告)日：2008-09-03

申请号：EP04785971

申请日：2004-06-30

Applicant: IBM

Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119

CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

Abstract translation: 场效应晶体管器件的多层栅电极堆叠结构形成在栅电介质（43）上的硅纳米晶种层（41）上。 使用原位快速热化学气相沉积（RTCVD），硅纳米晶体层的小晶粒尺寸允许沉积具有高达至少70％的[Ge]的均匀且连续的多晶SiGe（45）层。 在快速降低的温度下在氧气环境中原位净化沉积室导致SiO2或SixGeyOz薄界面层（47），（3）至4A厚。 薄SiO2或SixGeyOZ界面层足够薄且不连续以提供对栅极电流流动的小阻力，但具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴层发生硅化。 该栅极电极堆叠结构用于nFET和pFET。

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：EP1644968A4

公开(公告)日：2007-03-14

申请号：EP04777136

申请日：2004-06-25

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/336 ,  H01L20060101 ,  H01L21/20 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L29/785 ,  H01L21/2022 ,  H01L29/66795

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.