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1077 条记录 (耗时 0.027 秒)

    Bidirectional parallel signal interface
    21.
    发明公开
    Bidirectional parallel signal interface 失效
    Bidistktionale Parallelsignalschnittstelle

    公开(公告)号：EP1223515A2

    公开(公告)日：2002-07-17

    申请号：EP02004713.0

    申请日：1996-05-16

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Ballachino, William E. ,  Colgan, James A. ,  Jacobelli, Franco

    IPC分类号： G06F13/38

    CPC分类号： G06F13/38 ,  G06F13/385

    摘要： A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being control controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.

    摘要翻译： 用于在计算机和外部外围设备之间提供并行数据接口的双向并行信号接口包括具有用于传送命令和数据的命令寄存器的接口电路，用于在计算机和数据之间传送数据的先入先出（FIFO）存储器 外围设备，以及用于从命令寄存器接收命令的主机和从状态机，并且根据其控制FIFO和外围设备之间的数据通信，并向外部设备传送控制信号。 FIFO和外围设备之间的数据通信是根据命令寄存器的命令进行的。 主机和从机状态机的控制信号的通信响应于它们的控制信号，其响应性是根据来自命令寄存器的命令来控制的。 根据来自命令寄存器的命令，主机状态机停止从FIFO到外围设备的数据通信。 命令寄存器包括用于存储来自外围设备的数据的状态寄存器，其表示外围设备的状态数量。

    SELF-ALIGNED CMOS PROCESS
    23.
    发明授权
    SELF-ALIGNED CMOS PROCESS 失效
    自饰面CMOS工艺

    公开(公告)号：EP0715769B1

    公开(公告)日：2002-03-06

    申请号：EP94923248.2

    申请日：1994-06-24

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： DEMIRLIOGLU, Esin, Kutlu ,  ARONOWITZ, Sheldon

    IPC分类号： H01L21/225 ,  H01L21/82 ,  H01L21/336

    CPC分类号： H01L29/66575 ,  H01L21/2254 ,  H01L21/823835 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/66545

    摘要： A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.

    A VIRTUAL-GROUND FLASH EPROM ARRAY WITH REDUCED CELL PITCH IN THE X DIRECTION
    27.
    发明授权
    A VIRTUAL-GROUND FLASH EPROM ARRAY WITH REDUCED CELL PITCH IN THE X DIRECTION 失效
    与在X方向上减少细胞的步距虚拟地球FLASH EPROM MATRIX

    公开(公告)号：EP0698286B1

    公开(公告)日：2001-10-17

    申请号：EP95913692.0

    申请日：1995-03-13

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： BERGEMONT, Albert

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

    MOSFET WITH REDUCED LEAKAGE CURRENT
    28.
    发明授权
    MOSFET WITH REDUCED LEAKAGE CURRENT 失效
    MOSFET低漏电

    公开(公告)号：EP0756758B1

    公开(公告)日：2001-08-08

    申请号：EP96906497.1

    申请日：1996-02-14

    申请人： National Semiconductor Corporation

    发明人： LUICH, Thomas, M.

    IPC分类号： H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/8249 ,  H01L29/456

    摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current includes drain and source regions separated by a channel, a drain terminal over a portion of the drain region, a source terminal over a portion of the source region and a gate terminal opposite the channel. An oxide layer is deposited over the remaining portions of the drain and source regions, as well as on the adjacent vertical sides and top edges of the drain, source and gate terminals. A silicide layer is deposited over the gate terminal between the oxide-covered top edges thereof and over the drain and source terminal up to the oxide-covered top edges thereof. With oxide over the drain source regions instead of silicide, parasitic Schottky diodes are avoided, thereby eliminating leakage current due to such parasitic elements. Additionally, the oxide layer over the drain and source regions blocks pldd and nldd diffusions, thereby preventing impingement of the drain and source regions under the gate and adjacent oxide spacers and thereby significantly reducing leakage current due to band-to-band tunneling.

    TAMPER RESISTANT INTEGRATED CIRCUIT STRUCTURE
    29.
    发明授权
    TAMPER RESISTANT INTEGRATED CIRCUIT STRUCTURE 失效
    反对干预SECURED集成电路

    公开(公告)号：EP0710401B1

    公开(公告)日：2001-08-08

    申请号：EP94922017.2

    申请日：1994-06-24

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： BYRNE, Robert, C.

    IPC分类号： H01L27/02

    CPC分类号： H01L23/573 ,  H01L24/05 ,  H01L2924/14 ,  Y10S257/922 ,  H01L2924/00

    摘要： A tamper resistant structure has a pattern which covers portions of an IC but exposes other portions of the IC so that etching away the tamper resistant structure destroys the exposed portions. The IC can not be easily disassembled and reverse engineered because the tamper resistant structure hides active circuitry and removing the tamper resistant structure away destroys active circuitry. One embodiment of the tamper resistant structure includes a metal layer and a cap layer. The cap layer typically includes material that is difficult to remove, such as silicon carbide, silicon nitride, or aluminum nitride. The metal layer typically includes a chemically resistant material such as gold or platinum. A bonding layer of nickel-vanadium alloy, titanium-tungsten alloy, chromium, or molybdenum, may be used to provide stronger bonds between layers. Some embodiments provide an anti-corrosion seals for bonding pads in addition to the tamper resistant structure. The seals and tamper resistant structures are formed using the same materils and processing steps. The choice of pattern which covers and exposes different portions of the IC can be random or tailored to the active circuitry. The pattern can be the same for every chip or different for every chip formed from a wafer.