公开(公告)号：EP0978783A1

公开(公告)日：2000-02-09

申请号：EP99401474.4

申请日：1999-06-15

申请人： SCHLUMBERGER Systèmes

发明人： Fornas, Thierry M.

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4486

摘要： L'invention concerne un procédé de gestion de l'exécution concomitante, dans un dispositif à circuit intégré destiné à être intégré au sein d'un corps d'objet portatif, d'une part, d'un programme comprenant une ou plusieurs instructions, une des desdites instructions faisant appel à une ou plusieurs et, le cas échéant, à une ou plusieurs sous-routines, et, d'autre part, d'une instruction I x faisant appel à une ou plusieurs routines et, le cas échéant, à une ou plusieurs sous-routines selon lequel procédé, une adresse de la routine ou une adresse de la sous-routine, est enregistrée dans une première mémoire de sauvegarde d'adresses de retour. Selon l'invention, pour l'exécution du programme, une adresse ADD d'une instruction, une adresse d'une routine ou une adresse d'une sous-routine, est enregistrée dans une seconde mémoire de sauvegarde d'adresses de retour, la première mémoire de sauvegarde d'adresses de retour étant différente de la seconde mémoire de sauvegarde d'adresses de retour, et, en ce qu'on exécute une fonction de sauvegarde enregistrant une adresse d'une routine dans la seconde mémoire et réinitialisant la première mémoire de sauvegarde d'adresses de retour. L'invention s'applique, en particulier, aux modules d'identification abonnés SIM.

摘要翻译： 该方法涉及使用调用几个例程的程序，这些例程又调用子程序，子程序也可以调用子程序。 此外，可以同时向CPU做出其他指令。 当执行程序时，用于指令的地址存储在第一保护存储器中，并存储在附加的第二保护存储器中。 这两个记忆是独立的。

公开(公告)号：EP0514024A3

公开(公告)日：1994-05-04

申请号：EP92303551.3

申请日：1992-04-21

申请人： SUN MICROSYSTEMS, INC.

发明人： Frailong, Jean-Marc ,  Sindhu, Pradeep ,  Cekleov, Michel ,  Powell, Michael ,  Jenson, Eric

IPC分类号： G06F9/38

CPC分类号： G06F9/3004 ,  G06F9/30054 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0833

摘要： An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processors. The TSO memory model includes a FIFO Store Buffer for Store, and Atomic Load-Store operations. The Load operations are not placed in the FIFO Store Buffer. The Load operation checks for a value stored in the same location in the FIFO Store Buffer; if no such value is found, then requested value is returned from memory. The PSO model also includes a Store Buffer for Store, and Atomic Load-Store operations. However, unlike the TSO model, the Store Buffer in the PSO model is not FIFO. The processors in the PSO model may issue the Store and Atomic Load-Store in a certain order; however, such operations may be executed by memory out of the order issued by the processors. The execution order is assured only by address matching and the STBAR operation. Two Store operations separated by a STBAR operations guarantees memory will execute the operations in an order issued by the processors. Load operations in the PSO model are not placed in the Store Buffer. The Load operation first checks for a value stored in the same location in the Store Buffer; if no such value is found, then the requested value is returned from memory.

摘要翻译： 公开了改进的存储器模型和实现。 存储器模型包括总存储订购（TSO）和部分存储订购（PSO）存储器模型，以提供由多个处理器发出的存储器操作的部分订单。 TSO存储器模型包括用于存储的FIFO存储缓冲区和原子加载存储操作。 加载操作不在FIFO存储缓冲区中。 加载操作检查存储在FIFO存储缓冲区中相同位置的值; 如果没有找到这样的值，则从存储器返回所请求的值。 PSO模型还包括一个Store Store for Store和Atomic Load-Store操作。 但是，与TSO模型不同，PSO模型中的存储缓冲区不是FIFO。 PSO模型中的处理器可以按照特定顺序发布Store和Atomic Load-Store; 然而，这些操作可能会由处理器发出的命令执行。 执行顺序仅通过地址匹配和STBAR操作来保证。 由STBAR操作分隔的两个存储操作保证存储器将按照处理器发出的顺序执行操作。 PSO模型中的加载操作未放置在存储缓冲区中。 加载操作首先检查存储在存储缓冲区中相同位置的值; 如果没有找到这样的值，则从存储器返回所请求的值。

公开(公告)号：EP0547247A1

公开(公告)日：1993-06-23

申请号：EP92914444.0

申请日：1992-07-07

申请人： SEIKO EPSON CORPORATION

发明人： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  LAU, Tei-Li ,  TRANG, Quang, H.

IPC分类号： G06F9

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： Architecture de microprocesseur à mémoire centrale RISC haute performance comprenant une unité de lecture d'instructions permettant de lire des ensembles d'instructions dans une mémoire d'instructions et une unité d'exécution procédant à l'exécution simultanée de plusieurs instructions grâce à une disposition parallèle des unités fonctionnelles. L'unité de lecture conserve un nombre prédéterminé d'instructions dans une mémoire-tampon à instructions. L'unité d'exécution comporte une unité de sélection des instructions, couplée à la mémoire-tampon d'instructions et permettant de sélectionner les instructions pour exécution, et plusieurs unités fonctionnelles accomplissant des opérations fonctionnelles spécifiées par instructions. Un programmateur d'instructions unifiées, dans l'unité de sélection des instructions, amorce le traitement des instructions par les unités fonctionnelles lorsque les instructions sont déterminées disponibles pour exécution et lorsque au moins une des unités fonctionnelles assurant une fonction de calcul indispensable est disponible. La programmation unifiée est assurée par des cheminements multiples de données d'exécution, selon lesquels chaque cheminement de données d'exécution, et avec lui ses unités fonctionnelles correspondantes, est généralement optimisé pour le type de fonction de calcul à accomplir sur les données: intégrales, calcul en virgule flottante et algèbre de Boole. Le nombre, le type et les éléments spécifiques de calcul des unités fonctionnelles dans chaque cheminement de données, ainsi qu'entre ces cheminements, sont indépendants les uns des autres.

公开(公告)号：EP0111407B1

公开(公告)日：1992-04-29

申请号：EP83307317.4

申请日：1983-12-01

申请人： Bull HN Information Systems Inc.

发明人： Miu, Ming T. ,  Bradley, John J.

IPC分类号： G06F9/26

CPC分类号： G06F9/30054 ,  G06F9/268 ,  G06F9/4486

摘要： A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present routine, to a first register of a push down stack. In addition, the microcommand also pushes down one level the contents of all of the registers in the stack containing previously stored return addresses. Thus, a sequential return to unfinished routines or subroutines is provided. When the subroutine or hardware interrupt service routine is completed, a code in the address field enables the return address of the previously branched from or interrupted routine to be retrieved from the first register in the push down stack and to provide it as the address of the next instruction to be executed. The retrieval of the return address from the push down stack also pops all other stored return addresses one level in the stack. In addition to providing multiple levels of subroutine and interrupt nesting, any number of subroutines or hardware interrupts may be partially completed since the last operating subroutine or hardware interrupt service routine is always the first one to be completed. Logic is also provided to detect the occurrence of a hardware interrupt during a return sequence such that the requirement to simultaneously push and pop the stack is properly handled.

公开(公告)号：EP0465328A2

公开(公告)日：1992-01-08

申请号：EP91401780.1

申请日：1991-06-28

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Sites, Richard L. ,  Witek, Richard T.

IPC分类号： G06F9/38

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/324 ,  G06F9/342 ,  G06F9/3804 ,  G06F9/3846

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集限于寄存器到寄存器操作和寄存器加载/存储操作。 包括允许使用先前建立的数据结构的字节操作指令包括进行寄存器中字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。 提供加载/锁定和存储/条件指令允许实现原子字节写入。 通过提供条件移动指令，可以完全消除许多短分支。 条件移动指令测试寄存器，并且如果满足条件则将第二寄存器移动到第三寄存器; 该功能可以代替短分支，从而保持指令流的顺序性。 可以通过预测分支的目标并基于该预测预取新指令来加快性能; 遵循分支预测规则，要求将所有正向分支预测为未被采用，并且所有后向分支（如循环常见）被预测为采用。 另一个性能改进使得在标准尺寸的指令中使用未使用的位来提供用于跳转和跳转到子程序指令等的预期目标地址的提示。 因此，可以在实际地址计算并将其放入寄存器之前预取目标。 此外，跳转指令的未使用的位移部分可以包含一个字段来定义跳转的实际类型，即跳转，跳转到子程序，从子程序返回，从而将预测的目标地址放置在堆栈中，以便在 指令已执行。 处理器可以采用可变存储器页面大小，使得可以最佳地使用用于实现虚拟寻址的翻译缓冲器中的条目。 将一个粒度提示添加到页表项以定义该条目的页面大小。 另外的特征是添加预取指令，其用于在数据块被使用之前将数据块移动到存储器层级中的更快访问高速缓存。

公开(公告)号：EP0263447A3

公开(公告)日：1990-04-25

申请号：EP87114429.1

申请日：1987-10-02

申请人： International Business Machines Corporation

发明人： Crouse, Richard Stephen ,  Boudreaux, Randall Paul ,  Cazzolla, John Joseph, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/30054 ,  G06F8/66 ,  G06F9/322 ,  G06F9/328 ,  G06F9/4486

摘要： A digital data processor acts on a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. The operation code field of the branch and return on address instruction is into an instruction register, the memory exit address field of the loaded branch and return on address instruction is loaded into the address register and the memory entry address field of the branch and return on address instruction is loaded into the program counter. The next sequential address following the address of the current BAROA instruction is then stored in a register stack, and a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction is fetched and executed. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. The memory address in the program counter is compared with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.

公开(公告)号：EP0247146A1

公开(公告)日：1987-12-02

申请号：EP86907085.0

申请日：1986-10-30

申请人： MCC DEVELOPMENT, LTD.

发明人： MORRISON, Gordon, Edward ,  BROOKS, Christopher, Bancroft ,  GLUCK, Frederick, George

IPC分类号： G06F15 ,  G06F9

CPC分类号： G06F9/30054 ,  G06F8/445 ,  G06F8/45 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/4484 ,  G06F9/4486

摘要： In a data processing apparatus, a system for executing branches in single entry-single exit (SESE) basic blocks (BBs) contained within a program has means receiving the said program for determining a branch instruction within each basic block and for adding firing time information to the branch instruction. The firing time information identifies a time of execution of the branch instruction which is a variable number of instruction cycles prior to a time of execution of a last-to-be-executed instruction of the basic block. The system also has a processor operative on received non-branch instructions in each basic block for processing the instructions, and means operative on the received branch instruction in the basic block in response to the firing time information for completing the execution of said branch instruction no later than the same time as the processor is processing the last-to-be-executed non-branch instruction so that the execution of the branch instruction occurs in parallel with the execution of the non-branch instructions thereby speeding the overall processing of the program by the system.

公开(公告)号：EP0185215A2

公开(公告)日：1986-06-25

申请号：EP85114795.9

申请日：1985-11-21

申请人： HARRIS CORPORATION

发明人： Moore, Charles H. ,  Murphy, Robert W.

IPC分类号： G06F9/44

CPC分类号： G06F9/30134 ,  G06F8/31 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/321 ,  G06F9/3806 ,  G06F9/4486

摘要： A language specific microprocessor for the computer language known as FORTH is disclosed. The microprocessor includes four main registers each for holding a parameter; a L or instruction latch register for decoding instructions and activating microprocessor operation; an I or return index register for tracking returns; an N or next parameter register for operation with an arithmetic logic unit (ALU); and a T or top of parameter stack register with an appended ALU. A return stack port is connected to the I register and a parameter stack port is connected to the N register circuit, each have last in/first out (LIFO) memory stacks for reads and writes to isolated independent memory islands that are external to the microprocessor. The respective I, T and N registers are connected in respective series by paired bus connections for swapping parameters between adjacent registers. A first split 16 bit multiplexer J/K controls the LIFO stack for the I and N registers on paired 8 bit address stacks; a second 16 bit multiplexer designates the pointer to main memory with 65K addresses and an adjoining 65K for data. This addressing multiplexer receives selective input from a program counter P, the return index register the top of the parameter stack T and/or the instruction latch L. Movement to subroutine is handled in a single cycle with returns being handled at the end of any designated cycle. Asynchronous microprocessor operation is provided with the address multiplexer being simultaneously set up with an address to a future machine step, unloading from memory of appropriate data or instruction for the next machine step and asynchronously executing the current machine step. A two-phase clock latches data as valid on a rising edge and moves to a new memory location on a falling edge. This two phase clock is given a pulse width sufficient for all asynchronous cycles of microprocessor operations to settle. The microprocessor's assembler language is FORTH and the stack and main memory port architecture uniquely complements FORTH to produce a small (17,000 gates) fast (40 mips) microprocessor operable on extant FORTH programs. Provision is made for an additional G port which enables the current operating state of the microprocessor to be mapped, addressing of up to 21 bits as well as the ability to operate the microprocessor in tandem with similar microprocessors.

摘要翻译： 公开了一种称为FORTH的计算机语言的专用微处理器。 微处理器包括四个主寄存器，用于保存参数; L或指令锁存寄存器，用于解码指令并激活微处理器操作; 用于跟踪回报的I或返回索引寄存器; 用于与算术逻辑单元（ALU）一起操作的N或下一个参数寄存器; 和附加ALU的参数堆栈寄存器的T或顶部。 返回堆栈端口连接到I寄存器，参数堆栈端口连接到N寄存器电路，每个寄存器电路都有先进的（LIFO）存储器堆栈，用于读取写入到微处理器外部的独立独立存储器岛。 相应的I，T和N寄存器通过配对总线连接相互连接，用于在相邻寄存器之间交换参数。 第一个分裂16位多路复用器J / K控制配对8位地址堆栈上的I和N寄存器的LIFO堆栈; 第二个16位多路复用器指定具有65K地址的主存储器的指针和与数据相邻的65K。 该寻址复用器从程序计数器P，返回索引寄存器I，参数栈T的顶部和/或指令锁存器L接收选择性输入。在单个周期中处理移动到子程序，其中返回在 任何指定周期。 提供异步微处理器操作，地址多路复用器同时设置有未来机器步骤的地址，从存储器卸载适当的数据或下一个机器步骤的指令，并异步执行当前的机器步骤。 两相时钟在上升沿锁存数据为有效，并在下降沿移动到新的存储器位置。 给予这个两相时钟的脉冲宽度足以使所有的微处理器操作的异步循环结束。 微处理器的汇编语言是FORTH，并且堆栈和主存储器端口架构独特地补充了FORTH，以便产生一个可用于现存FORTH程序的小型（17,000门）快速（40mips）微处理器。 提供了一个额外的G端口，使得能够映射微处理器的当前操作状态，寻址高达21位以及与类似微处理器串联操作微处理器的能力。

公开(公告)号：EP1994471B1

公开(公告)日：2017-12-13

申请号：EP07762866.7

申请日：2007-02-01

申请人： Oracle America, Inc.

发明人： CAPRIOLI, Paul ,  CHAUDHRY, Shailender

IPC分类号： G06F12/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30054 ,  G06F12/0875 ,  G06F12/10 ,  G06F2212/655 ,  Y02D10/13

摘要： Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer can be avoided. Certain events, such as branch mis-predictions and exceptions, can be designated as page boundary crossing events. In addition, carry over at a particular bit position when computing a branch target or a next instruction instance fetch target can also be designated as a page boundary crossing event. An address translation buffer is accessed to translate an address representation of a first instruction instance. However, until a page boundary crossing event occurs, the address representations of subsequent instruction instances are not translated. Instead, the translated portion of the address representation for the first instruction instance is recycled for the subsequent instruction instances.

公开(公告)号：EP3234844A1

公开(公告)日：2017-10-25

申请号：EP15870567.3

申请日：2015-11-16

申请人： Intel Corporation

发明人： YAMADA, Koichi ,  BIJLANI, Ashish ,  LU, Jiwei ,  ZHAO, Cheng Yan

IPC分类号： G06F21/12 ,  G06F9/45

CPC分类号： G06F9/3806 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145

摘要： A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

摘要翻译： 描述了一种方法。 该方法包括：在确定该指令是返回指令时，接收指令，访问返回高速缓存以加载预测返回目标地址，在确定预测的已翻译返回目标地址不正确时，在查找表中搜索可执行二进制代码， 可执行的二进制代码来执行二进制转换。