公开(公告)号：EP3203504A1

公开(公告)日：2017-08-09

申请号：EP17153089.2

申请日：2017-01-25

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： YU, Guobin ,  XU, Xiaoping

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66818 ,  H01L29/66803 ,  H01L29/7856

摘要： The present invention provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.

摘要翻译： 本发明提供了半导体结构及其制造方法。 示例性制造方法包括提供半导体衬底; 在所述半导体衬底上形成多个鳍，每个鳍具有第一侧壁表面和相对的第二侧壁表面; 在所述鳍片上进行不对称氧化工艺，氧化所述鳍片的第一侧壁表面形成第一氧化层，并氧化所述鳍片的第二侧壁表面形成第二氧化层，所述第一氧化层的厚度不同 从所述第二氧化物层的厚度开始，并且所述第一氧化物层和所述第二氧化物层之间的所述鳍片的未氧化部分被配置为沟道层; 去除所述第二氧化物层和所述第一氧化物层的部分厚度; 以及在半导体衬底上方形成横跨沟道层的栅极结构。

公开(公告)号：EP3123518A1

公开(公告)日：2017-02-01

申请号：EP14887192.4

申请日：2014-03-27

申请人： Intel Corporation

发明人： CEA, Stephen, M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  RACHMADY, Willy ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818

摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

摘要翻译： 公开了用于将高迁移率应变通道结合到鳍状NMOS晶体管（例如，诸如双栅极，触发器等的FinFET）中的技术，其中将应力材料包覆到鳍的沟道区域上。 在一个示例性实施例中，锗或硅锗膜被包覆到硅散热片上，以便在翅片的芯中提供期望的拉伸应变，尽管可以使用其它翅片和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在典型工艺流程中的多个位置处。 在各种实施例中，可以以最小宽度（或稍后变薄）形成翅片，以便提高晶体管性能。 在一些实施例中，变薄的翅片还增加穿过包覆翅片的芯的拉伸应变。 在一些情况下，通过添加嵌入式硅外延源和漏极可以进一步增强芯中的应变。

公开(公告)号：EP3087590A1

公开(公告)日：2016-11-02

申请号：EP13900420.4

申请日：2013-12-23

申请人： Intel Corporation

发明人： GLASS, Glenn A. ,  MURTHY, Anand S. ,  AUBERTINE, Daniel B. ,  JOSHI, Subhash M.

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

摘要： Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

摘要翻译： 可以通过用于尺寸雕刻的射频（RF）等离子体和/或热处理来修改晶体管鳍元件（例如，鳍或三栅极）。 蚀刻的，变薄的翅片可以通过首先形成更宽的单晶翅片形成，并且在较宽翅片之间沉积沟槽氧化物材料之后，使用第二蚀刻来蚀刻较宽的翅片，以形成具有未损坏的顶部和侧壁的较窄的单晶翅片，用于外延生长活性 通道材料。 第二蚀刻可以去除顶表面和较宽翅片的侧壁之间的1nm和15nm之间的厚度。 它可以使用（1）使用低离子能量等离子体处理的氯或氟基化学物质去除厚度，或者（2）低温热处理，其不会通过能量离子轰击，氧化或留下蚀刻残留物而损坏翅片，这可能会破坏 外延生长质量的第二种材料。

公开(公告)号：EP2311077A1

公开(公告)日：2011-04-20

申请号：EP09788962.0

申请日：2009-07-21

申请人： Advanced Micro Devices, Inc.

发明人： LIN, Ming-ren ,  KRIVOKAPIC, Zoran ,  MASZARA, Witek

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.

公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

申请人： IBM

发明人： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC分类号： H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

摘要： The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP1588422A1

公开(公告)日：2005-10-26

申请号：EP04702507.7

申请日：2004-01-15

申请人： ADVANCED MICRO DEVICES, INC.

发明人： KRIVOKAPIC, Zoran ,  AN, Judy, Xilin ,  DAKSHINA-MURTHY, Srikanteswara ,  WANG, Haihong ,  YU, Bin

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

摘要： A narrow channel FinFET is described herein with a channel width of less than 6 nm. The FinFET may include a fin (140) in which the channel area is trimmed using a NH4OH etch or a reactive ion etch (RIE).

公开(公告)号：EP1532659A2

公开(公告)日：2005-05-25

申请号：EP03736783.6

申请日：2003-06-03

申请人： International Business Machines Corporation

发明人： FRIED, David M. ,  NOWAK, Edward, J. ,  RAINEY, Beth, Ann ,  SADANA, Devendra, K.

IPC分类号： H01L21/00

CPC分类号： H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

摘要： The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP3306665A3

公开(公告)日：2018-07-18

申请号：EP17195405.0

申请日：2017-10-09

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/0886 ,  H01L21/0276 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/12 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66818

摘要： A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the NMOS region and PMOS region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.

公开(公告)号：EP3238267A1

公开(公告)日：2017-11-01

申请号：EP14909247.0

申请日：2014-12-23

申请人： Intel Corporation

发明人： GARDNER, Sanaz K. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia ,  ZELICK, Nancy M. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

摘要： An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，该装置包括：包括上部和下部的翅片结构，上部具有与下部的上表面直接接触的底表面; 其中（a）下部包含在具有至少2：1的纵横比（深宽比）的沟槽中; （b）底面具有底部最大宽度，并且上表面具有底部最大宽度更大的上部最大宽度; （c）底面覆盖上表面的中间部分，但不覆盖上表面的侧面部分; （d）上部包括上部III-V族材料，下部包括不同于上部III-V族材料的下部III-V族材料。 这里描述了其他实施例。

公开(公告)号：EP3084812A4

公开(公告)日：2017-08-09

申请号：EP13899638

申请日：2013-12-16

申请人： INTEL CORP

发明人： CEA STEPHEN M ,  KOTLYAR ROZA ,  KENNEL HAROLD W ,  MURTHY ANAND S ,  GLASS GLENN A ,  KUHN KELIN J ,  GHANI TAHIR

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66818 ,  H01L29/7781 ,  H01L29/7782

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

摘要翻译： 涉及没有松弛衬底的应变NMOS和PMOS器件的技术和方法，包含这种半导体器件的系统及其方法。