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208 条记录 (耗时 0.012 秒)

    Method for forming semiconductor device isolation regions
    21.
    发明公开
    Method for forming semiconductor device isolation regions 失效
    形成半导体器件隔离区的方法

    公开(公告)号：EP0443879A2

    公开(公告)日：1991-08-28

    申请号：EP91301459.3

    申请日：1991-02-22

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Kawamura, Akio

    IPC分类号： H01L21/76 ,  H01L21/32

    CPC分类号： H01L21/76202 ,  H01L21/3088 ,  H01L21/32 ,  H01L21/76235 ,  Y10S148/05

    摘要： A method for forming semiconductor device isolation regions including steps of forming a first insulating film on a semiconductor substrate, removing the first insulating film in a portion to become a device isolation region with use of a resist pattern formed in an one-time lithography step as a mask so as to form an opening which reaches the semiconductor substrate, removing the resist pattern to deposit a second insulating film on the first insulating film and the inside of the opening and then etching the entire surface in order to make the second insulating film remain on only the periphery of the bottom of the opening and to expose the surface of the semiconductor substrate in a central portion of the bottom of the opening, forming an oxide film on the surface of the semiconductor substrate exposed in the central portion of the bottom of the opening with use of the first insulating film and the second insulating film on the periphery of the bottom of the opening as a mask by a selective oxidation method, removing the second insulating film on the periphery of the bottom of the opening and then etching the surface of the semiconductor substrate exposed on the periphery of the bottom of the opening with use of the oxide film formed in the central portion of the bottom of the opening by the selective oxidation method and the first insulating film which remains in portions other than the device isolation region as a mask so as to form a trench, and burying the trench with a third insulating film.

    摘要翻译： 一种用于形成半导体器件隔离区的方法，包括以下步骤：在半导体衬底上形成第一绝缘膜;使用在一次光刻步骤中形成的抗蚀剂图案，去除在成为器件隔离区的部分中的第一绝缘膜作为 以形成到达半导体基板的开口的掩模，去除抗蚀剂图案，在第一绝缘膜和开口内部沉积第二绝缘膜，然后蚀刻整个表面以便保留第二绝缘膜 仅在开口底部的周边上，并在开口底部的中心部分暴露出半导体衬底的表面，在半导体衬底的暴露在底部中心部分的表面上形成氧化膜 通过使用开口底部周围的第一绝缘膜和第二绝缘膜作为掩模的开口 采用有源氧化法，去除开口底部周围的第二绝缘膜，然后利用形成在开口底部中心部分的氧化膜蚀刻暴露在开口底部周围的半导体衬底表面 通过选择性氧化方法将开口的底部和保留在除器件隔离区之外的部分中的第一绝缘膜作为掩模以形成沟槽，并且用第三绝缘膜掩埋沟槽。

    Semiconductor device manufacturing process
    22.
    发明公开
    Semiconductor device manufacturing process 失效
    一种生产用于该方法的半导体装置和ERCVD设备处理。

    公开(公告)号：EP0424905A2

    公开(公告)日：1991-05-02

    申请号：EP90120394.3

    申请日：1990-10-24

    申请人： SONY CORPORATION

    发明人： Sato, Junichi, c/o Sony Corporation ,  Gocho, Tetsuo, c/o Sony Corporation ,  Morita, Yasushi, c/o Sony Corporation

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/00

    CPC分类号： H01L21/76229 ,  H01L21/31144 ,  Y10S148/05 ,  Y10S438/97

    摘要： A semiconductor device manufacturing process and a bias ECRCVD apparatus for carrying out the same. The semiconductor device manufac­turing process comprises steps of forming trenches in the surface of a substrate, forming an insulating film by bias ECRCVD over the surface of the substrate, etching the insulating film by lateral leveling etching to expand the width of grooves formed in portions of the insulating film formed in regions other than those corresponding to the trenches, masking the portions of the insulating film filling up the trenches and removing the portions of the insulating film formed in the regions other than those corresponding to the trenches. An etching stop layer is formed over the surface of the substrate before forming the trenches and the insulating film, and the etching stop layer is removed by etching after removing the portions of the insulating film formed in the regions other than those corresponding to the trenches by etching with the portions of the insulating film filling up the trenches masked.
    The surfaces of the portions of the insulating film filling up the trenches are finished flush with the surface of the substrate. Desirably, the etching stop layer is annealed to make the grains grow making the surface of the etching stop layer smooth to enable the complete removal of the portions of the insulating film formed in the regions other than those corresponding to the trenches.

    摘要翻译： 一种半导体器件的制造工艺以及用于执行该方法的偏压ECRCVD装置。 半导体器件制造方法包括在基材的表面形成沟槽，在基板的表面上的绝缘膜通过偏压ECRCVD的形成， - 由膜的横向平整蚀刻蚀刻绝缘扩大凹槽中的部分形成的宽度的步骤 绝缘膜形成在除那些对应于沟槽其他区域，掩蔽的部分上的绝缘膜填充了沟槽并除去绝缘膜形成在除那些对应于沟槽以外的区域的部分。 蚀刻停止层被形成沟槽和所述绝缘膜，电影之前形成的基材的表面上，并且蚀刻停止层通过去除绝缘膜形成在除那些由对应于沟槽以外的区域的部分之后刻蚀除去 与绝缘膜填充了沟槽的部分蚀刻掩蔽。 绝缘的部分的表面的膜填充沟槽完成齐平于基材的表面。 理想的是，蚀刻停止层进行退火，以使晶粒生长使蚀刻阻挡层光滑，以使完全除去在除那些对应于沟槽以外的区域的绝缘膜形成的部分的表面上。

    Nonvolatile semiconductor device and method of manufacturing the same
    23.
    发明公开
    Nonvolatile semiconductor device and method of manufacturing the same 失效
    非易失性半导体器件及其制造方法

    公开(公告)号：EP0410424A3

    公开(公告)日：1991-04-10

    申请号：EP90114270.3

    申请日：1990-07-25

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Yoshikawa, Kuniyoshi, c/o Intellectual Prop. Div.

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L29/0847 ,  H01L27/115 ,  H01L29/7885 ,  Y10S148/05

    摘要： A source diffusion region (104) and a drain diffusion region (102) are formed under an insulation film (106) which is thicker than a gate insulation film (107) and which isolates the adjacent channel regions (105) from each other. The adjacent source and drain diffusion regions (104, 102) are isolated from each other by a trench (103) which extends from the central portion of the thick insulation film (106) to the interior of a semiconductor substrate (101). The trench (103) is formed in a self-alignment manner with reference to the end portions of the adjacent floating gate electrodes (108), and the depth of this trench (103) is determined so that the adjacent source and drain diffusion regions (104, 102) can be spaced sufficiently apart from each other.

    Double wafer moated signal processor
    25.
    发明公开
    Double wafer moated signal processor 失效
    双波长运动信号处理器

    公开(公告)号：EP0317084A3

    公开(公告)日：1990-04-18

    申请号：EP88309838.6

    申请日：1988-10-20

    申请人： GRUMMAN AEROSPACE CORPORATION

    发明人： Solomon, Allen L.

    IPC分类号： H01L25/04 ,  H01L29/06

    CPC分类号： H01L25/50 ,  H01L21/76251 ,  H01L21/768 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/0002 ,  Y10S148/05 ,  Y10S148/085 ,  H01L2924/00

    摘要： The method of forming a multiwafer integrated circuit for abutting electrical connection to external electronics is disclosed. The method comprises forming a plurality of grooves (39, 41, 43, 45) in the first surface of each of first and second wafers (35, 37). The grooves are filled with a body of insulating material and joined along the groove surfaces thereof. In one embodiment active circuitry (46) is formed in one of the abutting wafer surfaces. In another embodiment active circuitry is formed in a non-abutting surface of one of the wafers. Conductive leads (48) are applied to the surface of one of the wafers to be in electrical communication with the doped regions (46). At least one of the conductive leads extends across at least a portion of the grooves. The wafers are trimmed in length so that the lengthwise edges of the wafers are defined by the grooves and the butt end of at least one of the conductive leads is exposed. A layer of conductive material is deposited along the lengthwise edge of the wafers in electrical communication with the exposed conductive lead to facilitate communication between the doped regions and external electronics.

    Integrated circuit isolation structure and method of making
    28.
    发明公开
    Integrated circuit isolation structure and method of making 失效
    集成电路隔离结构及其制作方法

    公开(公告)号：EP0166140A3

    公开(公告)日：1989-06-14

    申请号：EP85105716.6

    申请日：1985-05-10

    申请人： International Business Machines Corporation

    发明人： Beyer, Klaus Dietrich ,  Silvestri, Victor Joseph

    IPC分类号： H01L21/74 ,  H01L21/76

    CPC分类号： H01L21/743 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/763 ,  Y10S148/025 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/085

    摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer (28, 30, 31) is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body (12). A epitaxial layer (40) extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation: where y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer (46) fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer (40). A second insulating layer (48) is located on the polycrystalline silicon layer (46) within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor layer (40) which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer (46) above the epitaxial layer (40) completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.