-
公开(公告)号：EP3933567B1
公开(公告)日：2024-10-09
申请号：EP20926376.3
申请日：2020-11-20
CPC分类号： G06F12/0802 , G06F3/06 , G06F12/0882 , H03K19/17728 , G11C2029/041120130101 , G11C29/52 , G11C29/42 , G11C29/18 , G11C2029/180220130101 , G06F11/1048 , G11C2029/440220130101 , G11C29/4401
-
公开(公告)号：EP4439563A1
公开(公告)日：2024-10-02
申请号：EP23210878.7
申请日：2023-11-20
发明人： SEOK, Junyeong , SHIN, Beomkyu , OH, Eunchu
CPC分类号： G11C16/3454 , G11C16/16 , G11C16/14 , G11C16/3431 , G11C16/3427 , G11C16/3445
摘要： A memory block is divided into sub blocks including a first sub block and a second sub block that are disposed in a vertical direction where the memory block includes a plurality of cell strings and each cell string includes a plurality of memory cells that are disposed in the vertical direction. A normal erase operation is performed independently with respect to each of the sub blocks. A disturbance verification read operation with respect to the first sub block is performed to determine whether a threshold voltage of memory cells connected to a wordline in an erased state of the first sub block is increased higher than a reference level. A post erase operation is selectively performed based on a result of the disturbance verification read operation to decrease the threshold voltage of memory cells in the erased state of the first sub block.
-
23.发明公开
公开(公告)号：EP4439562A1
公开(公告)日：2024-10-02
申请号：EP24164846.8
申请日：2024-03-12
发明人： YANG, Kiyeon , GU, Dongggeon , KOO, Bonwon , PARK, Jeonghee , SUNG, Hajun , AHN, Dongho , WUN, Zhe , LEE, Changseung , CHOI, Minwoo
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C2213/7320130101 , G11C13/003 , G11C2213/7120130101
摘要： Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.
-
24.发明公开
公开(公告)号：EP4437542A1
公开(公告)日：2024-10-02
申请号：EP22921027.3
申请日：2022-01-18
发明人： HE, Youxin
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3459 , G11C16/102 , G11C2211/564120130101 , G11C16/32 , G11C29/52
-
公开(公告)号：EP4437537A1
公开(公告)日：2024-10-02
申请号：EP22817732.5
申请日：2022-11-15
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1675
-
公开(公告)号：EP3676843B1
公开(公告)日：2024-10-02
申请号：EP18852432.6
申请日：2018-08-29
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/20 , G11C16/28 , G11C16/3418 , G11C2211/564120130101 , G11C29/021 , G11C29/028 , G11C16/10 , G11C16/22 , G06F12/0246 , G06F2212/720720130101 , G06F2212/720220130101
-
27.发明公开
公开(公告)号：EP4436023A1
公开(公告)日：2024-09-25
申请号：EP23186014.9
申请日：2023-07-18
CPC分类号： H02M3/07 , H02M1/08 , H02M1/084 , H02M1/0845 , G11C5/145 , H03K5/1504 , H03K19/09429
摘要： The present disclosure relates to a charge pump circuit with a six-phase clock. The charge pump circuit comprises a six-phase clock circuit and a gate boosting charge pump configured to receive a plurality of clock signals from the six-phase clock circuit. The six-phase clock circuit includes provides a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, and a sixth clock signal. The gate boosting charge pump is configured to enable a charge-sharing operation to share the stored amount of charges between a plurality of parasitic capacitors. The six-phase clock circuit is configured to provide a dead time between each of the first, second, third, fourth, fifth and sixth clock.
-
28.发明公开
公开(公告)号：EP4435789A2
公开(公告)日：2024-09-25
申请号：EP24190820.1
申请日：2018-12-14
发明人： FENG, Xuehuan , LI, Yongqian
IPC分类号： G11C19/28
CPC分类号： G11C19/28 , G09G2310/028620130101 , G09G2310/026720130101 , G09G3/3266 , G09G3/3674
摘要： A shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit includes a blanking input circuit (100), a display input circuit (200), an output circuit (300), a first control circuit (500) and a second control circuit (600). The blanking input circuit (100) inputs a blanking pull-up signal to a first node (Q) according to a blanking input signal; the display input circuit (200) inputs a display pull-up signal to the first node (Q) in response to a display input signal; the output circuit (300) outputs an composite output signal to an output terminal (Out) under the control of the first node (Q); the first control circuit (500) controls a level of a second node (QB) under the control of the first node (Q); and the second control circuit (600) controls the level of the second node (QB) in response to a blanking pull-down control signal.
-
公开(公告)号：EP4433330A1
公开(公告)日：2024-09-25
申请号：EP22896558.8
申请日：2022-11-18
发明人： CAIN, Jr., Edward Allen , PATNE, Satyajit P. , BARKER, Russell K. , WILSON, Ryan N. , THANICKEL, Ismail
IPC分类号： B60R16/023 , G06F3/06 , G06F16/23 , G11C27/00
CPC分类号： H04L67/06 , H04L67/1097 , H04L67/145 , G06F8/654 , G06F9/4401
-
公开(公告)号：EP3764362B1
公开(公告)日：2024-09-25
申请号：EP20169744.8
申请日：2020-04-16
IPC分类号： G11C11/16 , H10B61/00 , H10N50/10 , H01L23/522
CPC分类号： G11C11/161 , H01L23/5226 , H10B61/00 , H10N50/10
-
-
-
-
-
-
-
-
-
搜索结果
33273 条记录 (耗时 0.032 秒)
