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151 条记录 (耗时 0.01 秒)

    Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB)
    33.
    发明公开
    Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) 审中-公开
    Verfahren zur Plattierung von Verbindungsschichten auf einem Leitermuster einer Leiterplatte

    公开(公告)号：EP1381260A1

    公开(公告)日：2004-01-14

    申请号：EP02254876.2

    申请日：2002-07-11

    申请人： Ultratera Corporation

    发明人： Maa, Chong-Ren ,  Chih, Wan-Kuo ,  Tsou, Ching-Hua

    IPC分类号： H05K3/24 ,  H05K3/28

    CPC分类号： H05K3/242 ,  H05K3/0041 ,  H05K3/243 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/0554 ,  H05K2203/066 ,  H05K2203/1152 ,  H05K2203/1572

    摘要： A method of plating connecting layers (the Ni-Au layers) on a conductor pattern of a printed circuit board (PCB) comprises the steps of: A. Prepare a substrate (10) with a conductor pattern (20) thereon. B. Coat a masking layer (30) onto the substrate (10), wherein the conductor pattern (20) is sheltered by the masking layer (30) but exposed at plating portions (24) and conductive portions (22) thereof. C. Plate a conductive layer (50) onto the masking layer (30), wherein the conductive layer (50) is electrically connected with the conductor pattern (20) at the conductive portions (22). D. Coat a second masking layer (60) onto the conductive layer (50), wherein the plating portions (24) of the conductor pattern (20) are exposed. E. Adding voltage to the conductive layer (50) to plate connecting layers (70) onto the plating portions (24) of the conductor pattern (20) respectively. F. Remove the second masking layer (60), and G. Remove the conductive layer (50).

    摘要翻译： 在印刷电路板（PCB）的导体图案上电镀连接层（Ni-Au层）的方法包括以下步骤：A.在其上制备具有导体图案（20）的基板（10）。 B.将掩模层（30）涂覆到基板（10）上，其中导体图案（20）被掩模层（30）遮盖，但在其镀层部分（24）和导电部分（22）处露出。 C.将导电层（50）放置在掩模层（30）上，其中导电层（50）在导电部分（22）处与导体图案（20）电连接。 D.将第二掩模层（60）涂覆到导电层（50）上，其中导体图案（20）的镀覆部分（24）暴露。 E.向导电层（50）施加电压以将连接层（70）分别压到导体图案（20）的镀覆部分（24）上。 F.拆下第二掩模层（60），并拆下导电层（50）。

    Apparatus and method for vacuum lamination of adhesive film
    35.
    发明公开
    Apparatus and method for vacuum lamination of adhesive film 审中-公开
    方法和装置用于真空层叠粘接薄膜

    公开(公告)号：EP1095766A3

    公开(公告)日：2002-08-14

    申请号：EP00309545.2

    申请日：2000-10-30

    申请人： Ajinomoto Co., Inc.

    发明人： Nakamura, Shigeo, c/o Aminoscience Laboratories

    IPC分类号： B32B31/20 ,  H05K3/00

    CPC分类号： H05K3/281 ,  B32B37/0053 ,  B32B2457/08 ,  H05K3/4661 ,  H05K2203/066 ,  H05K2203/068 ,  H05K2203/085

    摘要： Herein is disclosed an apparatus for vacuum lamination of an adhesive film wherein the resin composition layer of an adhesive film is vacuum laminated continuously on the patterned part of a circuit board by heating and pressing conditions with the use of a heat-resistant rubber roll, said heat-resistant rubber roll being wider than said adhesive film, and having concave parts or notch parts corresponding to the width of the adhesive film to be placed and on the surfaces in the vicinity of both the ends of the roll. The present invention relates to an apparatus and method for vacuum lamination of an adhesive film wherein the problem of fouling a laminating roll caused by the seepage of the resin composition from an adhesive film for circuit board lamination can be obviated, whereby the problem of fouling a laminating roll caused by the seepage of the resin composition from an adhesive film for circuit board lamination at the lamination can be solved.

    Method of fabricating a laminated circuit assembly and product thereof
    36.
    发明公开
    Method of fabricating a laminated circuit assembly and product thereof 审中-公开
    Verfahren zur Herstellung einer laminierten Schaltungsanordnung und erhaltenes Produkt

    公开(公告)号：EP1085789A2

    公开(公告)日：2001-03-21

    申请号：EP00119863.9

    申请日：2000-09-13

    申请人： MOLEX INCORPORATED

    发明人： Bablee, Bruno ,  Malone, Michael

    IPC分类号： H05K3/00 ,  H05K7/02

    CPC分类号： H05K3/0058 ,  H05K3/386 ,  H05K2201/0909 ,  H05K2201/2009 ,  H05K2203/0264 ,  H05K2203/066 ,  Y10T156/1052 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1062 ,  Y10T156/1074 ,  Y10T428/15 ,  Y10T428/24314 ,  Y10T428/24777

    摘要： A method of fabricating a laminated circuit assembly and the assembly made therefrom including the steps of providing a relatively stiff substrate. A U-shaped slit is cut in the substrate in an area where a peripheral pull tab subsequently is to be located. The side legs of the U-shaped configuration define spaced slit portions. A relatively flexible backing sheet is adhered to a back side of the substrate. The laminated substrate and backing sheet are cut with a peripheral cut intersecting the side legs of the U-shaped slit, with the peripheral cut forming a pull tab projecting outwardly from the U-shaped slit. The pull tab can be grasped and separated from the substrate to strip the backing sheet therefrom.

    摘要翻译： 一种制造层叠电路组件的方法和由其制成的组件包括提供相对刚性的基板的步骤。 在随后将要设置外围拉片的区域中的基板上切割出U形狭缝。 U形构造的侧腿限定了间隔开的狭缝部分。 相对柔性的背衬片粘附到基底的背面。 层叠基材和背衬片用与U形狭缝的侧腿相交的周边切口切割，周边切口形成从U形狭缝向外突出的拉片。 拉片可以被抓握并与基底分离以从其剥离背衬片。