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    Control method and apparatus for a plurality of memory units
    41.
    发明公开
    Control method and apparatus for a plurality of memory units 失效
    Steuerungsverfahren und -einrichtungfüreine Vielzahl von Speichereinheiten。

    公开(公告)号：EP0066147A2

    公开(公告)日：1982-12-08

    申请号：EP82104206.6

    申请日：1982-05-13

    Applicant: NEC CORPORATION

    Inventor： Chiwaki, Yoshinori

    IPC: G06F11/20

    CPC classification number: G11C29/74 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/141 ,  G06F13/1684 ,  G11C29/28

    Abstract: The invention relates to a control method and apparatus for a plurality of memory units installed in a data processing system. In the control method a plurality of memory units (4, 5) perform simultaneous writing or reading operations, one of the memory units (4;5) being selected for normal use. In the event of an error occurring during a write mode operation, a memory unit (4;5) without error is immediately selected alternatively, and in the event of an error during a read mode operation the selection is made in response to the next clock pulse to permit a retry from a processor (1 ;2). The control apparatus comprises a plurality of memory units (4, 5), memory unit access means (12), a plurality of error holding circuits (17, 18), control means (23), status selection commanding means (13), and status selector means (14). The control method and apparatus works with enhanced reliability and performance.

    Abstract translation: 本发明涉及一种安装在数据处理系统中的多个存储单元的控制方法和装置。 在控制方法中，多个存储器单元（4,5）执行同时的写入或读取操作，其中一个存储器单元（4; 5）被选择用于正常使用。 在写入模式操作期间发生错误的情况下，交替地立即选择没有错误的存储器单元（4; 5），并且在读取模式操作期间发生错误的情况下，响应于下一个时钟进行选择 脉冲以允许从处理器（1; 2）重试。 控制装置包括多个存储单元（4,5），存储单元访问装置（12），多个错误保持电路（17,18），控制装置（23），状态选择指令装置（13）和 状态选择装置（14）。 控制方法和设备具有更高的可靠性和性能。

    DUTY-CYCLE-EFFICIENT SRAM CELL TEST
    45.
    发明公开
    DUTY-CYCLE-EFFICIENT SRAM CELL TEST 有权
    - 关于向占空比的高效SRAM单元测试

    公开(公告)号：EP1415305A2

    公开(公告)日：2004-05-06

    申请号：EP02787139.1

    申请日：2002-07-11

    Applicant: International Business Machines Corporation ,  Compagnie IBM France

    Inventor： NELSON, Erik.A ,  PILO,Harold

    IPC: G11C29/00

    CPC classification number: G11C29/28 ,  G11C29/34

    Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

    Semiconductor memory with built-in parallel bit test mode
    47.
    发明公开
    Semiconductor memory with built-in parallel bit test mode 失效
    半导体存储器内置的并行Bitprüfmodus

    公开(公告)号：EP0929077A3

    公开(公告)日：2000-06-07

    申请号：EP99104096.5

    申请日：1994-01-03

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Ohsawa, Takashi ,  Fujii, Shuso

    IPC: G11C29/00 ,  G11C7/00 ,  G11C11/409

    CPC classification number: G11C29/28 ,  G11C29/08 ,  G11C29/24 ,  G11C29/34 ,  G11C29/40 ,  G11C29/44

    Abstract: A semiconductor memory comprising a memory cell block 111 comprising a plurality of memory cells, having n pairs of parallel bit structure; two pairs of word lines WL connected to said memory cells of said memory cell block; n pairs of bit lines BL, /BL connected to said memory cells of said memory cell block; n pairs of DQ data lines DQ05, /DQ05 - DQ35, /DQ35 connected to said n pairs of bit lines and divided into two groups each comprising n/2 pairs of the DQ data lines, a group of n/2 pairs of the DQ lines being arranged at a side of said memory cell block and another group of n/2 pairs of the DQ lines being arranged at an opposite side of said memory cell block.

    SCHALTUNGSANORDNUNG FÜR EINEN PROGRAMMIERBAREN NICHTFLÜCHTIGEN SPEICHER
    48.
    发明公开
    SCHALTUNGSANORDNUNG FÜR EINEN PROGRAMMIERBAREN NICHTFLÜCHTIGEN SPEICHER 失效
    电路装置的可编程非易失性存储器

    公开(公告)号：EP0883878A1

    公开(公告)日：1998-12-16

    申请号：EP97915310.0

    申请日：1997-02-27

    Applicant: SIEMENS AKTIENGESELLSCHAFT

    Inventor： GEORGAKOS, Georg ,  KERN, Thomas ,  SOMMER, Diether ,  ZETTLER, Thomas

    IPC: G11C16 ,  G11C29

    CPC classification number: G11C29/28 ,  G11C16/10

    Abstract: A circuit configuration for a programmable nonvolatile memory having memory cells organized in rows and columns, includes a programming circuit which contains a first device for testing purposes that applies a programming current to a first predetermined number of memory cells in parallel for a first predetermined time period. During a second predetermined time period, the device thereupon connects a second predetermined number, which is greater than the first number, in parallel an applies the programming current to them. A method is provided for operating the circuit configuration.

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