公开(公告)号：EP2553730A2

公开(公告)日：2013-02-06

申请号：EP11766306.2

申请日：2011-02-16

Applicant: Freescale Semiconductor, Inc.

Inventor： KHEMKA, Vishnu K. ,  KHAN, Tahir A. ,  HUANG, Weixiao ,  ZHU, Ronghua

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/098 ,  H01L27/0705 ,  H01L27/085 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80') coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage V
DS exceeds the switch's (80, 80') threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801', 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70', 90, 90') by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.

公开(公告)号：EP2058854A3

公开(公告)日：2012-03-21

申请号：EP08167263.6

申请日：2008-10-22

Applicant: Acreo AB

Inventor： Bakowski, Mietek ,  Schöner, Adolf ,  Ericsson, Per

IPC: H01L21/82 ,  H01L27/06 ,  H01L27/07 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L21/8213 ,  H01L27/0623 ,  H01L27/0705 ,  H01L29/1608 ,  H01L29/66068

Abstract: A semiconductor device of SiC is formed by a cascode arrangement of a Bipolar Junction Transistor (BJT) and a Junction Field Effect Transistor (JFET) interconnecting a first (1) and a second (12) terminal of the device. The device has a buried grid adapted to form a pn-junction at a distance below the active region of the BJT while taking a major part of the voltage drop across said terminals in the blocking state of the semiconductor device, so that in spite of such a device designed for high voltages the BJT may be designed for low voltages.

Abstract translation: SiC的半导体器件由互连器件的第一（1）和第二（12）端子的双极结晶体管（BJT）和结型场效应晶体管（JFET）的共源共栅布置形成。 该器件具有埋入式栅极，该栅极适于在BJT的有源区下方的一定距离处形成pn结，同时在半导体器件的阻断状态下占据跨过所述端子的电压降的大部分，使得尽管如此 为高电压而设计的器件BJT可以设计用于低电压。

公开(公告)号：EP2093799A3

公开(公告)日：2010-03-10

申请号：EP09162684.6

申请日：2002-08-16

Applicant: Power Integrations, Inc.

Inventor： Disney, Donald Ray

IPC: H01L27/07

CPC classification number: H01L27/0705 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/49113 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

公开(公告)号：EP1791181B1

公开(公告)日：2010-02-03

申请号：EP05425835.5

申请日：2005-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Cappelletti, Paolo Giuseppe

IPC: H01L27/07 ,  H01L21/8249 ,  H01L27/24

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

公开(公告)号：EP1309006B1

公开(公告)日：2009-06-17

申请号：EP02255727.6

申请日：2002-08-16

Applicant: Power Integrations, Inc.

Inventor： Disney, Donald Ray

IPC: H01L27/07

CPC classification number: H01L27/0705 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/49113 ,  H01L2924/13091 ,  H01L2924/00

公开(公告)号：EP1526576A3

公开(公告)日：2007-11-07

申请号：EP04012376.2

申请日：2004-05-25

Applicant: Marvell World Trade Ltd.

Inventor： Sutardja, Sehat

IPC: H01L27/088 ,  H01L27/07

CPC classification number: H01L29/0847 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78

Abstract: An integrated circuit comprises a first source and a first drain. A first gate is arranged between the first source and the first drain. A first body is arranged inside of and is surrounded by the first source. Alternately, an integrated circuit comprises a first source and a first drain. A first gate is arranged between the first source and the first drain. A first body is arranged inside of and is surrounded by the first source. A second gate is arranged between the first source and the second drain. The first source includes a source contact tap. The first and second gates are arranged farther apart adjacent to the source contact tap than in areas that are not adjacent to the source contact tap.

公开(公告)号：EP1684356A3

公开(公告)日：2006-11-29

申请号：EP06009436.4

申请日：2003-12-04

Applicant: Micrel, Inc.

Inventor： Mallikarjunaswamy, Shekar

IPC: H01L29/732 ,  H01L29/10

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0705 ,  H01L27/0744 ,  H01L29/0692 ,  H01L29/1004 ,  H01L29/7322 ,  H01L29/7378 ,  H01L29/7393

Abstract: A bipolar transistor (100) formed on a p-type substrate 102 comprises a base region 108, an emitter region 106 and a collector region 110, with a diffusion region 114 in the collector region and having a conductivity type opposite to the conductivity type of the collector region.

Abstract translation: 双极晶体管（100）包括形成在基极区域（108）中的辅助扩散区域（116），其具有与基极区域相反的导电类型并且电耦合到基极区域。 或者，辅助扩散区域可以形成在辅助扩散区域具有与集电极区域相反的导电类型的集电极区域中，并且电耦合到集电极区域。 辅助扩散区域在双极晶体管中形成次级寄生晶体管，其具有抑制由与双极晶体管相关联的初级寄生双极型器件引起的寄生双极性导通的作用。

公开(公告)号：EP1684356A2

公开(公告)日：2006-07-26

申请号：EP06009436.4

申请日：2003-12-04

Applicant: Micrel, Inc.

Inventor： Mallikarjunaswamy, Shekar

IPC: H01L29/732 ,  H01L29/10

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0705 ,  H01L27/0744 ,  H01L29/0692 ,  H01L29/1004 ,  H01L29/7322 ,  H01L29/7378 ,  H01L29/7393

Abstract: A bipolar transistor (100) formed on a p-type substrate 102 comprises a base region 108, an emitter region 106 and a collector region 110, with a diffusion region 114 in the collector region and having a conductivity type opposite to the conductivity type of the collector region.

Abstract translation: 形成在p型衬底102上的双极晶体管（100）包括基极区域108，发射极区域106和集电极区域110，在集电极区域中具有扩散区域114，并具有与导电类型相反的导电类型 收藏家地区。

公开(公告)号：EP1642339A1

公开(公告)日：2006-04-05

申请号：EP04743314.9

申请日：2004-07-08

Applicant: SEIKO EPSON CORPORATION

Inventor： CHU, Daping Cambridge Research Laboratory of Epson

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/78612 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78696

Abstract: A semiconductor device comprising an n-channel region and a p-channel region formed on a common substrate, both channel regions having a source and a drain, the device further comprising a gate electrode common to both channel regions and spaced from the substrate by an area of non-polarising dielectric material arranged under the gate electrode.

Abstract translation: 一种半导体器件，包括在公共衬底上形成的n沟道区和p沟道区，两个沟道区都具有源极和漏极，所述器件还包括栅极，所述栅极对于两个沟道区域是公共的并且通过 布置在栅电极下方的非偏振电介质材料的面积。

公开(公告)号：EP1071109A4

公开(公告)日：2003-07-09

申请号：EP99909285

申请日：1999-03-19

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： KOGA KEISUKE

IPC: H01J1/304 ,  H01L27/07 ,  H01J1/30 ,  H01L27/06

CPC classification number: H01L27/0705 ,  H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

Abstract: A field-emission electron source which comprises a field-emission electron source part formed on a p-type silicon substrate (1) and an n-channel field-effect transistor part formed on the p-type silicon substrate (1) in a position corresponding to the field-emission electron source part and in which the field-emission electron source part is provided in the drain region of the field-effect transistor part, and the field-emission current from the field-emission source part is controlled by a control voltage applied to the gate electrode (8) of the field-effect transistor part, wherein the drain region includes at least two wells (3, 4) with different impurity concentrations, the well (4) having the lower impurity concentration is provided at an end part of the drain region provided in contact with the channel region of the field-effect transistor part.