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332 条记录 (耗时 0.023 秒)

    CONFIGURABLE ACCELERATOR FRAMEWORK, SYSTEM AND METHOD
    67.
    发明公开
    CONFIGURABLE ACCELERATOR FRAMEWORK, SYSTEM AND METHOD 审中-公开

    公开(公告)号：EP3346427A1

    公开(公告)日：2018-07-11

    申请号：EP17197155.9

    申请日：2017-10-18

    申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    发明人： BOESCH, Mr. Thomas ,  DESOLI, Mr. Giuseppe

    IPC分类号： G06N3/063 ,  G06N3/04

    CPC分类号： G06N3/063 ,  G06N3/0454

    摘要： Embodiments are directed towards a configurable accelerator framework device (400) that includes a stream switch (500) and a plurality of convolution accelerators (600). The stream switch (500) has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators (600) is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators (600) is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.

    HARDWARE ACCELERATOR ENGINE AND METHOD
    68.
    发明公开
    HARDWARE ACCELERATOR ENGINE AND METHOD 审中-公开

    公开(公告)号：EP3346425A1

    公开(公告)日：2018-07-11

    申请号：EP17197096.5

    申请日：2017-10-18

    申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    发明人： BOESCH, Mr. Thomas ,  DESOLI, Mr. Giuseppe

    IPC分类号： G06N3/063 ,  G06N3/04

    CPC分类号： G06N3/063 ,  G06N3/0454

    摘要： Embodiments are directed towards a hardware accelerator engine (600) that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators (600A), and each one of the plurality of convolution accelerators (600A) includes a kernel buffer (616), a feature line buffer (618), and a plurality of multiply-accumulate (MAC) units (620). The MAC units (620) are arranged to multiply and accumulate data received from both the kernel buffer (616) and the feature line buffer (618). The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.

    RADIO-FREQUENCY IDENTIFICATION TRANSPONDER AND METHOD FOR DATA TRANSMISSION BY MEANS OF RADIO-FREQUENCY IDENTIFICATION TECHNOLOGY
    69.
    发明公开
    RADIO-FREQUENCY IDENTIFICATION TRANSPONDER AND METHOD FOR DATA TRANSMISSION BY MEANS OF RADIO-FREQUENCY IDENTIFICATION TECHNOLOGY 审中-公开
    VERFAHREN ZURDATENÜBERTRAGUNGMITTELS FUNKFREQUENZIDENTIFIKATIONSTECHNOLOGIE的RADIOQUEZZENENTIFIKATIONSTRANSPONDER

    公开(公告)号：EP3121755A1

    公开(公告)日：2017-01-25

    申请号：EP15177652.3

    申请日：2015-07-21

    申请人： STMicroelectronics International N.V.

    发明人： Kovacic, Kosta ,  Pevec, Albin ,  Stiglic, Maksimiljan

    IPC分类号： G06K7/00 ,  G06K19/07 ,  G06K19/077 ,  H04B1/7183 ,  H04B5/00

    CPC分类号： H04B5/0068 ,  G06K7/0008 ,  G06K19/0715 ,  G06K19/0723 ,  G06K19/07749

    摘要： An RFID transponder comprises a coding and modulation unit (CMU) designed to generate a transmission signal (S_t) by modulating an oscillator signal (S_o) with an encoded bit signal (S_e). During a first and a second time segment (T1, T2), the encoded bit signal (S_e) assumes a first and a second logic level, respectively. The transmission signal (S_t) comprises a first signal pulse (P1) featuring a first phase within the first time segment (T1) and a second signal pulse (P2) featuring a second phase being shifted with respect to the first phase by a predefined phase difference within the second time segment (T2). The transmission signal (S_t) is paused for a pause period (TP) between the first and the second signal pulse (P1, P2), the pause period (TP) being shorter than a mean value of a period of the first and a period of the second time segment (T1, T2).

    摘要翻译： RFID应答器包括通过用编码比特信号（S_e）调制振荡器信号（S_o）而被设计来生成发送信号（S_t）的编码和调制单元（CMU）。 在第一和第二时间段（T1，T2）期间，编码比特信号（S_e）分别呈现第一和第二逻辑电平。 传输信号（S_t）包括第一信号脉冲（P1），其特征在于第一时间段（T1）内的第一相位和第二信号脉冲（P2），其特征在于第二相位相对于第一相位移位预定相位 第二时间段（T2）之间的差异。 发送信号（S_t）在第一和第二信号脉冲（P1，P2）之间的暂停时段（TP）中暂停，暂停时段（TP）比第一和第二信号脉冲 的第二时间段（T1，T2）。