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公开(公告)号：EP4414870A1
公开(公告)日：2024-08-14
申请号：EP24155671.1
申请日：2024-02-05
Applicant: STMicroelectronics International N.V.
Inventor： TROTTIER, Gilles
CPC classification number: G06F21/51 , G06F21/575
Abstract: La présente description concerne un procédé comprenant l'exécution, par un processeur (104) d'un dispositif de traitement (100), d'un code de démarrage afin de réaliser une séquence de démarrage du dispositif de traitement, l'exécution comprenant :
- au moins une étape de vérification du bon déroulement de la séquence de démarrage ; et
- si l'au moins une étape de vérification identifie une erreur dans le déroulement de la séquence de démarrage, le stockage d'une valeur de statut dans un registre (114) du dispositif de traitement et la réinitialisation du dispositif de traitement, le registre (114) étant accessible en lecture par l'intermédiaire d'une interface de débogage (112) du dispositif.-
公开(公告)号：EP4414802A1
公开(公告)日：2024-08-14
申请号：EP24154344.6
申请日：2024-01-29
Applicant: STMicroelectronics International N.V.
Inventor： RIZZARDINI, Federico , BRACCO, Lorenzo
CPC classification number: G05B23/024 , G06N3/08
Abstract: A sensor unit (102) is coupled to a machine (100) and configured to detect anomalous behavior of the machine (100). The sensor unit (102) includes a low power microcontroller that learns to recognize a plurality of operations of the machine (100). The sensor unit (102) generates mean vector (M) and inverse of a Cholesky decomposition matrix for each operation. During a detection mode the sensor unit (102) computes a Mahalanobis distance for each feature vector (F), mean vector (M) and first matrix. The sensor unit (102) detects anomalous behavior or classifies the operation of the machine (100) based on the Mahalanobis distances.
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63.发明公开
公开(公告)号：EP4411814A1
公开(公告)日：2024-08-07
申请号：EP24150220.2
申请日：2024-01-03
Applicant: STMicroelectronics International N.V.
Inventor： MAZZOLA, Mauro , MARCHISI, Fabio
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L23/49562 , H01L23/49524 , H01L24/37 , H01L24/40 , H01L24/84 , H01L2224/4024720130101 , H01L2224/4024820130101 , H01L2224/4024920130101 , H01L2224/3701320130101 , H01L2224/400520130101 , H01L2224/400720130101 , H01L24/48 , H01L24/743
Abstract: A semiconductor die (14) is arranged at a die mounting location (12A) of a substrate (12). The substrate (12) comprises an array of electrically conductive leads (12B) at the periphery of the substrate (12) .
Electrical coupling is provided between the semiconductor die (14) and selected ones of the electrically conductive leads (12B) in the array of electrically conductive leads (12B) via electrically conductive ribbons (20) having a body portion (200) having a first width (W1) as well as first and second end portions (201) bonded to the semiconductor die (14) and to the electrically conductive leads (12B), respectively.
At least one of the first and second end portions (201) of the electrically conductive ribbons (20) comprises a tapered portion having a second width (W2) smaller than the first width (W1) of the body portion (200) .-
公开(公告)号：EP4404065A1
公开(公告)日：2024-07-24
申请号：EP23220123.6
申请日：2023-12-22
Applicant: STMicroelectronics International N.V.
Inventor： GOYAL, Avneep Kumar , ANAND, Amritanshu , MALHI, Satinder Singh
CPC classification number: G06F11/3648 , G06F11/3636 , G06F11/1441
Abstract: An apparatus (100) comprises debug circuitry (104) configured to perform debug operations on a processing system (106), and reset circuitry (102) configured to generate a trace and debug reset signal (110) and a main reset signal (112) based at least in part on an invoke reset signal (108). The main reset signal (112) is communicated to elements of the processing system (106), and the trace and debug reset signal (110) is communicated to elements of the debug circuitry (104).
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公开(公告)号：EP4390733A1
公开(公告)日：2024-06-26
申请号：EP23217123.1
申请日：2023-12-15
Applicant: STMicroelectronics International N.V.
CPC classification number: G06F21/85 , G06F21/572 , G06F21/44 , G06F21/71 , G06F21/62
Abstract: A System-on-Chip (SoC) device (1) includes at least one core (2), a plurality of peripherals (4, 42, 402, 421, 422) and at least one bus (3) for interconnecting the core (2) and the peripherals (4). Some peripherals (421) can be selectively enabled or disabled on demand. The SoC device (1) further includes a peripheral enabling/disabling electronics (6A, 6B, 6C, 6D) and a peripheral enabling/disabling circuitry (5) coupled to the peripherals (421) . The peripheral enabling/disabling electronics is directly connected to the peripheral enabling/disabling circuitry and is configured to: store information items related to a enabled/disabled peripheral configuration and indicating the peripherals (421) that are enabled and the peripherals (421) that are disabled according to the enabled/disabled peripheral configuration; and provide the peripheral enabling/disabling circuitry (5) with signals based on the stored information items. The peripheral enabling/disabling circuitry allows operation of the peripherals (421) that are enabled and prevent operation of the peripherals (421) that are disabled based on the signals received from the peripheral enabling/disabling electronics. The peripheral enabling/disabling electronics implements a secure mechanism allowing access to the peripheral enabling/disabling electronics and modification of the stored information items only if security criteria are met.
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Patent Agency Ranking
公开(公告)号：EP4386860A1
公开(公告)日：2024-06-19
申请号：EP23213901.4
申请日：2023-12-04
Applicant: STMicroelectronics International N.V.
Inventor： CONSTANT, Aurore , IUCOLANO, Ferdinando , TRINGALI, Cristina
IPC: H01L29/778 , H01L21/337 , H01L23/29 , H01L23/31 , H01L29/41 , H01L29/10 , H01L29/20
CPC classification number: H01L29/66462 , H01L29/7786 , H01L29/2003 , H01L29/404 , H01L23/291 , H01L29/1066 , H01L29/408 , H01L23/3192 , H01L23/3171
Abstract: La présente description concerne un transistor HEMT comportant :
- une première couche semiconductrice (13) ;
- une grille (15) disposée sur une première face de la première couche semiconductrice (13) ;
- une première couche de passivation (17) en un premier matériau sur les flancs de la grille, la première couche de passivation se prolongeant en outre sur une première partie de ladite face de la première couche semiconductrice ; et
- une deuxième couche de passivation (19) en un deuxième matériau différent du premier matériau sur une deuxième partie de ladite face de la première couche semiconductrice à côté de la première couche de passivation.-
67.发明公开
公开(公告)号：EP4383318A1
公开(公告)日：2024-06-12
申请号：EP23214558.1
申请日：2023-12-06
Applicant: STMicroelectronics International N.V.
Inventor： MAZZOLA, Mauro
IPC: H01L21/56 , H01L23/498 , H01L21/48 , H01L23/495
CPC classification number: H01L23/49861 , H01L23/49541 , H01L21/561 , H01L21/4842
Abstract: A common electrically conductive substrate (12) is provided for a plurality of semiconductor devices. The common substrate (12) comprises a plurality of substrate portions (12A, 12B) configured (12A) to host at least one respective semiconductor chip (14). The adjacent substrate portions (12A, 12B) have mutually facing sides with elongate sacrificial connecting bars (CB) extending between the mutually facing sides. The electrically conductive substrate (12) is cut (SL) along the length of the elongate sacrificial connecting bars (CB) to provide singulated individual substrate portions (12A, 12B). The elongate sacrificial connecting bars (CB) are provided with an apertured structure comprising apertures (100) distributed along the length of the elongate sacrificial connecting bars (CB) wherein the apertures (100) provide zones of reduced resistance to cutting.
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公开(公告)号：EP4346066A2
公开(公告)日：2024-04-03
申请号：EP23191906.9
申请日：2023-08-17
Inventor： KARUPPUSAMY, Baranidharan , BHANUSHALI, Abhay Jaisen
Abstract: A method for operating a wireless power transmitter includes: receiving a power control command from a wireless power receiver; computing a potential voltage change for a transmitter voltage of the wireless power transmitter in accordance with a target transmitter power and a present value of a transmitter current of the wireless power transmitter; comparing the potential voltage change with a discrete step size of a supply voltage; and in response to determining that the magnitude of the potential voltage change is equal to or larger than the discrete step size of the supply voltage, adjusting the transmitter power by: adjusting the supply voltage by one or more discrete steps; and controlling a power conversion circuit of the wireless power transmitter using a target current value computed in accordance with the target transmitter power and the adjusted supply voltage.
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公开(公告)号：EP4307304A2
公开(公告)日：2024-01-17
申请号：EP23174861.7
申请日：2023-05-23
Applicant: STMicroelectronics International N.V.
Inventor： DHORI, Kedar Janardan , RAWAT, Harsh , KUMAR, Promod , CHAWLA, Nitin , AYODHYAWASI, Manuj
IPC: G11C7/10 , G06N3/063 , G11C11/419
Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
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公开(公告)号：EP4300496A1
公开(公告)日：2024-01-03
申请号：EP23174864.1
申请日：2023-05-23
Applicant: STMicroelectronics International N.V.
Inventor： DHORI, Kedar Janardan , RAWAT, Harsh , KUMAR, Promod , CHAWLA, Nitin , AYODHYAWASI, Manuj
Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.
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