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178 条记录 (耗时 0.013 秒)

    C-axis oriented lead germanate film and deposition method
    61.
    发明公开
    C-axis oriented lead germanate film and deposition method 审中-公开
    C-Axen-orientierter Bleigermanat-Film和Abscheidungsmethode

    公开(公告)号：EP1049148A2

    公开(公告)日：2000-11-02

    申请号：EP00303640.7

    申请日：2000-04-28

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Li, Tingkai ,  Zhang, Fengyan ,  Ono, Yoshi ,  Hsu, Sheng Teng

    IPC分类号： H01L21/316

    CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

    摘要： A ferroelectric Pb 5 Ge 3 O 11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1 x 10 8 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6 x10 -7 A/cm 2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb 5 Ge 3 O 11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

    摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均晶粒尺寸为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些薄膜还显示出无疲劳特性：在1×10 8个切换周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

    ESD protection thyristor with trigger diode
    62.
    发明公开
    ESD protection thyristor with trigger diode 有权
    带触发二极管的ESD保护晶闸管

    公开(公告)号：EP0982776A3

    公开(公告)日：2000-11-02

    申请号：EP99306769.3

    申请日：1999-08-25

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Kawazoe, Hidechika ,  Aoki, Eiji ,  Hsu, Sheng Teng ,  Fujii, Katsumasa

    IPC分类号： H01L27/02 ,  H01L29/74

    CPC分类号： H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L29/7412

    摘要： An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode (A) for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region (9); a p-type anode high impurity concentration region (10); and an insulator section (12,13,14) for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

    摘要翻译： 根据本发明的静电放电保护装置设置在半导体集成电路的输入端或输出端，用于保护半导体集成电路的内部电路免受流入或流出半导体集成电路的静电冲击。 该静电放电保护装置包括：晶闸管; 和触发二极管（A），用于触发具有低电压的晶闸管。 触发二极管包括：n型阴极高浓度杂质区域（9）; p型阳极高杂质浓度区域（10）; 以及绝缘体部分（12,13,14），用于使在n型阴极高杂质浓度区域的表面上形成的硅化物层与在p型阳极高杂质浓度区域的表面上形成的另一硅化物层电绝缘。

    Alkene ligand precursor and synthesis method
    63.
    发明公开
    Alkene ligand precursor and synthesis method 有权
    烯烃配体前体和合成方法

    公开(公告)号：EP1001047A3

    公开(公告)日：2000-05-31

    申请号：EP99308880.6

    申请日：1999-11-08

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Zhuang, Wei-Wei ,  Nguyen, Tue ,  Evans, David R. ,  Hsu, Sheng Teng ,  Barrowcliff, Robert ,  Charneski, Lawrence J.

    IPC分类号： C07F1/08 ,  C07F15/00 ,  C07F1/00 ,  C23C16/18

    CPC分类号： C23C16/18

    摘要： A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C 1 to C 8 alkyl, C 1 to C 8 haloalkyl, and C 1 to C 8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.

    摘要翻译： 已经提供了金属（hfac），烯烃配体前体。 烯烃配体包括双键碳原子，其中第一和第二键连接到第一碳原子，第三和第四键连接到第二碳原子。 第一，第二，第三和第四键选自H，C1至C8烷基，C1至C8卤代烷基和C1至C8烷氧基。 作为一般类别，尽管在低温下在液相中稳定，但这些前体能够具有高金属沉积速率和高挥发性。 用该前体沉积的铜具有低电阻率和高粘合特性。 已经提供了产生上述烯烃配体类别的金属前体的高收率的合成方法。

    Metal gate sub-micron mos transistor and method of making same
    64.
    发明公开
    Metal gate sub-micron mos transistor and method of making same 审中-公开
    金属栅极亚微米晶体管及其制造方法

    公开(公告)号：EP0929105A3

    公开(公告)日：1999-12-22

    申请号：EP99300130.4

    申请日：1999-01-08

    申请人： Sharp Kabushiki Kaisha ,  SHARP MICROELECTRONICS TECHNOLOGY, INC.

    发明人： Hsu, Sheng Teng ,  Nguyen, Tue ,  Evans, David R.

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423

    CPC分类号： H01L29/6659 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/82385 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

    摘要： A MOS transistor is formed on a single crystal silicon substrate doped to form a conductive layer of a first type, and includes: an active region formed on said substrate; a source region and a drain region located in said active region, doped to form conductive channels of a second type; a metal gate region located in said active region between said source region and said drain region, wherein said metal gate has a width of less than one micron; a gate oxide region located over said gate region; an oxide region located over the structure; and a source electrode, a gate electrode and a drain electrode, each connected to their respective regions, and each formed of a combination of a contact metal and an electrode metal. An alternate embodiment includes a pair of MOS transistors which have an interconnect between their gate electrodes and the drain electrode of one transistor and the drain electrode of the other transistor.

    摘要翻译： MOS晶体管形成在掺杂以形成第一类型的导电层的单晶硅衬底上，并且包括：在所述衬底上形成的有源区; 位于所述有源区中的源极区和漏极区，被掺杂以形成第二类型的导电沟道; 位于所述源极区和所述漏极区之间的所述有源区中的金属栅极区，其中所述金属栅极具有小于1微米的宽度; 位于所述栅极区域上方的栅极氧化物区域; 位于结构上的氧化物区域; 以及分别连接到它们各自的区域的源电极，栅电极和漏电极，并且每一个由接触金属和电极金属的组合形成。 另一个实施例包括一对MOS晶体管，它们在其栅极和一个晶体管的漏极和另一个晶体管的漏极之间具有互连。

    A method of forming an ultra-thin soi electrostatic discharge protection device
    66.
    发明公开
    A method of forming an ultra-thin soi electrostatic discharge protection device 有权
    Herstellungsverfahrenfüreineultradünne，elektrostatische SOI-Entladungsschutzvorrichtung

    公开(公告)号：EP0959497A1

    公开(公告)日：1999-11-24

    申请号：EP99302108.8

    申请日：1999-03-18

    申请人： Sharp Kabushiki Kaisha ,  SHARP MICROELECTRONICS TECHNOLOGY, INC.

    发明人： Hsu, Sheng Teng

    IPC分类号： H01L21/84 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A method of forming, on an ultra-thin SOI substrate, an ESD protected device, includes: preparing a single crystal silicon substrate, including forming insulated areas thereon and forming selectively conductive areas thereon; doping the selectively conductive layers with dopants; growing, epitaxially, silicon layers over selected insulated areas and the doped, selectively conductive areas; heating the substrate and the structures formed thereon at between about 850° C to 1150° C for between about 30 minutes to three hours to redistribute the dopant into the epitaxially grown silicon layer; completing the fabrication of additional layers in the structure; and metallizing the structure.

    摘要翻译： 在超薄SOI衬底上形成ESD保护器件的方法包括：制备单晶硅衬底，包括在其上形成绝缘区域并在其上形成选择性导电区域; 用掺杂剂掺杂选择性导电层; 在选定的绝缘区域上生长，外延硅层，以及掺杂的选择性导电区域; 将衬底及其上形成的结构在约850℃至1150℃之间加热约30分钟至3小时，以将掺杂剂重新分配到外延生长的硅层中; 完成结构中附加层的制造; 并对结构进行金属化。

    Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing
    67.
    发明公开
    Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing 有权
    使用化学机械研磨方法与铁电单晶体管存储单元的制造方法

    公开(公告)号：EP0923117A1

    公开(公告)日：1999-06-16

    申请号：EP98309917.7

    申请日：1998-12-03

    申请人： Sharp Kabushiki Kaisha ,  SHARP MICROELECTRONICS TECHNOLOGY, INC.

    发明人： Evans, David R. ,  Lee, Jong Jan ,  Hsu, Sheng Teng

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/51

    CPC分类号： H01L29/66477 ,  H01L29/78391

    摘要： A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.

    摘要翻译： 构建单晶体管铁电存储器（FEM）单元包括的方法，包括：制备用于结构的FEM栅极单元的硅衬底; 形成栅极，源区和漏区上的硅衬底; 形成在该结构上，以预定的厚度等于用于FEM栅极单元的底部电极的规定厚度的氮化物层; 上方形成的结构的第一绝缘层; 化学机械抛光检查的第一绝缘层做其顶面是即使在氮化物层的顶部; 形成用于FEM细胞底电极; 和化学机械抛光检查的底部电极那样其顶面是即使在第一绝缘层的顶表面。 附加层被抛光，以及形成，这取决于FEM小区的特定最终配置。