公开(公告)号：EP0223694A2

公开(公告)日：1987-05-27

申请号：EP86402472.4

申请日：1986-11-04

申请人： FAIRCHILD SEMICONDUCTOR CORPORATION

发明人： Burton, Gregory N.

IPC分类号： H01L21/306 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/30604 ,  H01L21/76264 ,  H01L21/76281 ,  Y10S148/05 ,  Y10S148/116

摘要： To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitax­ial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is then filled with a suitable insulating material to isolate the active island from the substrate.

公开(公告)号：EP0162711A3

公开(公告)日：1986-05-28

申请号：EP85303599

申请日：1985-05-22

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Horioka, Keiji c/o Patent Division ,  Okano, Haruo c/o Patent Division ,  Sekine, Makoto c/o Patent Division

IPC分类号： H01L21/314 ,  C23C08/36

CPC分类号： H01L21/02238 ,  C04B41/4505 ,  C04B41/81 ,  C23C8/04 ,  C23C16/047 ,  H01L21/02255 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76224 ,  H01L21/76281

摘要： @ An insulation layer (43) is selectively formed by exposing the surface of a workpiece (41) to an atmosphere comprising a mixture of a halogen-based gas and a raw gas containing a compoundable element chemically bondable with an element of a material constituting surface layer of the workpiece (41) to form an insulating compound. The surface layer of the workpiece (41) is formed of a non-insulating material, such as a metallic material or a semiconductor material. Light rays are directly irradiated on the selected region or regions of the surface of the workpiece (41) through the atmosphere of the gaseous mixture, thereby dissociating the halogen-based gas. As a result, a layer (43) comprising the insulating compound is formed on the selected region of the surface of the workpiece (41) on which the light rays have been directly irradiated.

公开(公告)号：EP0159655A2

公开(公告)日：1985-10-30

申请号：EP85104594.8

申请日：1985-04-17

申请人： International Business Machines Corporation

发明人： Kinney, Wayne Irving ,  Lasky, Jerome Brett ,  Nesbit, Larry Alan

IPC分类号： H01L21/76 ,  H01L21/306

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76281 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

摘要： A method is provided for forming semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions (30) and a set of surface regions (50) having characteristics which make them anodically etch slower than the remaining portion of the silicon body (10). These two sets of regions define portions (32, 52, 62) in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions (50) from each other and the remaining portion (62) of the silicon body. Typically in a P-type silicon body the buried and surface regions (30, 50) are N-type regions formed through ion implantation. Using these N-type regions to control the exposure of the P-type material to the anodic etching solution and the formation of the porous silicon regions, a structure is obtained wherein surface monocrystalline silicon regions are isolated from the rest of the silicon body by a uniform layer of silicon dioxide (62) having a predetermined thickness.

公开(公告)号：EP0135401A1

公开(公告)日：1985-03-27

申请号：EP84401208.8

申请日：1984-06-13

申请人： SGS-THOMSON MICROELECTRONICS S.A.

发明人： Borel, Joseph

IPC分类号： H01L21/76 ,  H01L21/20

CPC分类号： H01L21/02667 ,  H01L21/2022 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  Y10S148/011

摘要： @ La présente invention concerne un procédé de fabrication de composants semiconducteurs isolés sur une plaquette semiconductrice du type utilisé en technologie bipolaire. Selon ce procédé, du silicium polycristallin (7) est déposé dans un évidement (10) d'un substrat de silicium dont les parois sont isolées par une couche de nitrure de silicium (6) à l'exception d'une ouverture (20) formée dans cette couche de nitrure au fond de l'évidement. Ensuite, le silicium polycristallin est réépitaxié pour devenir du silicium monocristallin par échauffement thermique à partir du "germe" constitué par le silicium sous-jacent dans l'ouverture (20).
Application à la fabrication de transistors PNP latéraux.

公开(公告)号：EP0059264A1

公开(公告)日：1982-09-08

申请号：EP81110369.6

申请日：1981-12-11

申请人： Rockwell International Corporation

发明人： Soclof, Sidney Isaac

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L29/06

CPC分类号： H01L29/6625 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/735

摘要： The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ which is driven in from one side only while N+ is introduced and driven in from both sides, thereby providing an N+ P+P, N+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

摘要翻译： 本发明提供了一个独特的亚微米尺寸的NPN型晶体管及其制造寻求晶体管的相同worin狗红色的方法可以与每个晶体管包括由场氧化物包围有源区的单个芯片上制造的完全呼叫从底物和其影响分离它 上操作。 在基板许可证角度蒸发制成槽蚀刻的抗蚀剂，而将其从基板通过经由狭槽蚀刻其下方断开以保护有源区。 基底氧化支持而正交时隙上提供允许进入有源区的相对侧上用于掺杂P +有源区域的所有其在从一侧仅在N +被引入并从bothsides在驱动，由此在N + P + P提供驱动， N +发射极，基极，集电极晶体管有源区到哪个电连接，使用Applied的常规技术，从而提供由于从衬底的有源区域的总氧化物隔离的寄生电容和termoresistencias的几乎完全还原。

公开(公告)号：EP2455967B1

公开(公告)日：2018-05-23

申请号：EP11152112.6

申请日：2011-01-25

申请人： IMEC VZW

发明人： Kar, Gouri Sankar ,  Cacciato, Antonio ,  Kim Min-Soo

IPC分类号： H01L21/762 ,  H01L27/11521 ,  H01L21/8234

CPC分类号： H01L21/76224 ,  H01L21/76208 ,  H01L21/76281 ,  H01L21/823431 ,  H01L27/11521

摘要： The present invention is related to a method for forming a buried dielectric layer underneath a semiconductor fin. The method involves forming fins in semiconductor substrate by forming trenches in the substrate, depositing insulation material in said trenches and partially removing said material from the trenches, where after a liner is produced on the sidewalls of the trenches and top layer of the insulating material is furthermore removed, so as to reveal a window at the sidewalls of a bottom regions of the fin(s). Through said window, the material of the fins is transformed into a dielectric material, while the rest of the fin is protected, to thereby form a buried dielectric layer. The method can further comprise steps to form hybrid bulk/SOI substrate or steps to form a floating gate memory device.

公开(公告)号：EP2757581A1

公开(公告)日：2014-07-23

申请号：EP13192567.9

申请日：2013-11-12

申请人： NXP B.V.

发明人： Spaan, Erik ,  Van Dalen, Rob ,  Boos, Priscilla

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC分类号： H01L27/0623 ,  H01L21/76221 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7302

摘要： There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer. The taper of the tapered insulating layer is in the lower surface of the tapered insulating layer. The tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer.

摘要翻译： 公开了一种半导体器件。 该装置包括：硅层; 形成在硅层上的锥形绝缘层; 以及形成在锥形绝缘层上方的多个双极CMOS DMOS器件层。 锥形绝缘层的锥度位于锥形绝缘层的下表面。 锥形绝缘层具有基本平坦的上表面并且至少部分地凹入硅层中。

公开(公告)号：EP2519967A2

公开(公告)日：2012-11-07

申请号：EP10841770.0

申请日：2010-12-30

申请人： Solexel, Inc.

发明人： MOSLEHI, Mehrdad, M. ,  WANG, David, Xuan-Qi

IPC分类号： H01L21/677 ,  H01L21/683

CPC分类号： H01L21/6833 ,  G03F7/70708 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/6831 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76879 ,  H02N13/00 ,  Y02P80/30

摘要： In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode regions separated by a frontside trench through the top semiconductor layer extending at least to an underlying insulating layer positioned between the top semiconductor layer and a bottom semiconductor layer. A dielectric layer covers the top exposed surfaces of the carrier. Backside trenches through the bottom semiconductor layer extending at least to the insulating layer form isolated backside regions corresponding to the frontside positive and negative electrode regions. Backside contacts positioned on the bottom semiconductor layer and coupled to the positive and negative electrode regions allow for the electric charging of the frontside electrode regions.

公开(公告)号：EP1804281A1

公开(公告)日：2007-07-04

申请号：EP05425930.4

申请日：2005-12-28

申请人： STMicroelectronics S.r.l.

发明人： Colombo, Roberto

IPC分类号： H01L21/3065 ,  H01L21/762

CPC分类号： H01L21/30655 ,  H01L21/76281 ,  H01L21/76283

摘要： A process for digging deep trenches in a body of semiconductor material envisages: forming a mask (3) having at least one opening (5), above a surface (2a) of a semiconductor body (2); forming a passivating layer (6, 6') conformally on the mask (3) and on the semiconductor body (2) within the opening (5); executing a directional etch so as to first remove the passivating layer (6, 6') at least from on top of the semiconductor body (2) and then etch the semiconductor body (2) through the opening (5). The steps of forming a passivating layer (6, 6') and executing a directional etch are carried out repeatedly in sequence so as to form a trench (10) through the opening (5). In a step of the process, moreover, a tapered portion (10") of the trench (10) is formed, which has a transverse dimension (W") decreasing as a distance (D) from the surface (2a) of the semiconductor body (2) increases.

摘要翻译： 一种用于在半导体材料的主体挖掘深沟槽方法设想：形成掩模（3），其具有半导体主体（2）中的至少一个开口（5），上述的表面（2A）; 形成钝化层（6，6“）共形地在掩模（3）和在所述半导体主体（2）的开口（5）内; 执行定向刻蚀以便首先从在半导体主体（2）的顶部去除负债至少婷层（6，6“），然后通过所述开口（5）蚀刻半导体主体（2）。 形成钝化层婷（6，6“）和执行定向蚀刻的步骤被顺序重复进行，以便形成通过所述开口（5）的沟槽（10）。 在该方法的一个步骤，更上方，锥形部分（10“）的沟槽（10）的形成，其具有横向尺寸（W”半导体的）降低从所述表面（2A）的距离（D） 体（2）增加。

公开(公告)号：EP0708980B1

公开(公告)日：2000-01-19

申请号：EP94920168.5

申请日：1994-06-10

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： REEDY, Ronald, E. ,  BURGENER, Mark, L.

IPC分类号： H01L21/20 ,  H01L29/78

CPC分类号： H01L28/20 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/86 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  Y10S148/15 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S438/977