公开(公告)号：EP3042390A1

公开(公告)日：2016-07-13

申请号：EP13892844.5

申请日：2013-09-04

申请人： Intel Corporation ,  Goel, Niti ,  Pathi, Pragyansri ,  Dasgupta, Sansaptak ,  Powers, James M. ,  Chu-kung, Benjamin ,  Chau, Robert S.

发明人： MUKHERJEE, Niloy ,  GOEL, Niti ,  GARDNER, Sanaz K. ,  PATHI, Pragyansri ,  METZ, Matthew V. ,  DASGUPTA, Sansaptak ,  SUNG, Seung Hoon ,  POWERS, James M. ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

IPC分类号： H01L21/20

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

摘要翻译： 设置的沟槽（与用于形成沟槽的过程）并减少或防止在类型III-V族或锗（Ge）材料（E. G.，“缓冲”材料）的选择性外延生长晶形缺陷从基片材料的顶表面上。 缺陷可能是由与侧壁氧化物沟槽侧壁选择性外延生长的碰撞。 搜索沟槽包括（I）在以40度和70度之间的角度具有倾斜的沟槽侧壁：相对于表面的基材;（E. G，如55度）。 和/或（2）具有组合沟槽上沟槽上方和周围的下部沟槽的开口（例如，下沟槽可以具有倾斜侧壁，短的垂直壁，或高的竖直壁）。 这些沟槽减小或防止在外延侧壁生长缺陷，其中生长触及或生长针对它在生长在沟槽的垂直侧壁。

公开(公告)号：EP2943974A1

公开(公告)日：2015-11-18

申请号：EP13870795.5

申请日：2013-09-13

申请人： LG Siltron Inc.

发明人： SIM, Woo-Young

IPC分类号： H01L21/20

CPC分类号： H01L22/10 ,  C30B15/203 ,  C30B29/06 ,  C30B31/04 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/3225 ,  H01L21/324 ,  H01L29/32

摘要： A silicon single crystal wafer comprises an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

公开(公告)号：EP1801854B1

公开(公告)日：2015-06-24

申请号：EP05783304.8

申请日：2005-09-16

申请人： Shin-Etsu Handotai Co., Ltd.

发明人： YOKOKAWA, Isao, c/o Shin-Etsu Handotai Co. Ltd. ,  NOTO, Nobuhiko, c/o Shin-Etsu Handotai Co. Ltd. ,  MITANI, Kiyoshi, c/o Shin-Etsu Handotai Co. Ltd.

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L27/12

CPC分类号： C30B33/06 ,  C30B29/30 ,  C30B29/32 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02694

公开(公告)号：EP2624451A4

公开(公告)日：2015-03-11

申请号：EP11829169

申请日：2011-09-28

申请人： MURATA MANUFACTURING CO

发明人： ITO KOREKIYO

IPC分类号： H03H9/25 ,  H01L41/08 ,  H01L41/22 ,  H01L41/312 ,  H01L41/316 ,  H01L41/332 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02 ,  H03H9/05 ,  H03H9/17

CPC分类号： H01L41/253 ,  H01L21/02694 ,  H01L41/0536 ,  H01L41/081 ,  H01L41/0815 ,  H01L41/0838 ,  H01L41/18 ,  H01L41/27 ,  H01L41/277 ,  H01L41/297 ,  H01L41/312 ,  H01L41/332 ,  H01L41/47 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02574 ,  H03H9/059 ,  H03H9/173

摘要： Disclosed is a piezoelectric device free of some problems associated with ion implantation: the degradation of the surface roughness of the piezoelectric thin film and the cracking of the supporting substrate. Also disclosed is a method for manufacturing this piezoelectric device. During an isolation formation step a supporting substrate (50) has a piezoelectric thin film (10) formed on its front (14) with a compressive stress film (90) present on its back (15). The compressive stress film (90) compresses the surface (14 on the piezoelectric single crystal substrate (1) side of the supporting substrate (50), and the piezoelectric thin film (10) compresses the back (15) of the supporting substrate (50), which is opposite to the surface (14) on the piezoelectric single crystal substrate (1) side. In other words, the compressive stress produced by the compressive stress film (90) and that by the piezoelectric thin film (10) are in balance in the supporting substrate (50). This makes the supporting substrate (50) free of warpage and able to remain flat. To this end, the driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film (10).

摘要翻译： 公开的是自由的与离子注入相关的一些问题的压电装置，上述压电薄膜的表面粗糙度和支撑基板的裂纹的恶化。 所以圆盘游离缺失是用于制造该压电器件的方法。 在形成过程中的分离步骤与压缩应力膜（90）上存在的它的后面（15）的支撑基板（50）具有形成在其前表面（14）的压电薄膜（10）。 压缩应力电影（90）压缩所述表面（14在压电单晶衬底（1）的支撑基板（50）的侧上，并且压电薄膜（10）压缩所述支撑基板的背面（15）（50 ），所有这些是相对在压电单晶衬底（1）侧。换句话说，由压缩应力成膜所产生的压缩应力（90）的表面（14）和由所述压电薄膜（10所做的那样）是在 在支撑基板（50）的平衡。这使得在支撑基板（50）自由弯曲的和能够保持平坦的。为此，驱动力确实诱导隔离在隔离形成步骤是注入离子化元件的气化，而不是 压缩应力由压电薄膜（10）中产生的绝缘平面。

公开(公告)号：EP2474039A4

公开(公告)日：2014-01-08

申请号：EP10814561

申请日：2010-09-03

申请人： VISHAY SILICONIX

发明人： LU HAMILTON ,  CHAU THE-TU ,  TERRILL KYLE ,  PATTANAYAK DEVA N ,  SHI SHARON ,  CHEN KUO-IN ,  XU ROBERT

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/2205 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

摘要： Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

摘要翻译： 衬底晶片背面和边缘截面密封件的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 晶片也可以被植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：EP1573791A2

公开(公告)日：2005-09-14

申请号：EP03814644.5

申请日：2003-12-02

申请人： International Business Machines Corporation

发明人： COHEN, Guy, M. ,  CHRISTIANSEN, Silke, H.

IPC分类号： H01L21/20

CPC分类号： H01L21/76243 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624

摘要： A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer.

公开(公告)号：EP0660380B1

公开(公告)日：1999-06-09

申请号：EP94309534.9

申请日：1994-12-20

申请人： NATIONAL RESEARCH COUNCIL CANADA

发明人： Charbonneau, Sylvain ,  Koteles, Emil S.

IPC分类号： H01L21/22 ,  H01L33/00 ,  H01S3/19

CPC分类号： B82Y20/00 ,  G02B6/1347 ,  G02B2006/12169 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02694 ,  H01L21/182 ,  H01S5/3413 ,  H01S5/3414

公开(公告)号：EP0708980A1

公开(公告)日：1996-05-01

申请号：EP94920168.0

申请日：1994-06-10

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： REEDY, Ronald, E. ,  BURGENER, Mark, L.

IPC分类号： H01L21 ,  H01L27 ,  H01L29 ,  H04Q9

CPC分类号： H01L28/20 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/86 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  Y10S148/15 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S438/977

摘要： A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

摘要翻译： 在蓝宝石芯片上的单个超薄硅上提出了一种高频无线通信系统。 该系统在蓝宝石芯片上的单个超薄硅上集成了模拟，数字（逻辑和存储器）和高射频电路。 使用传统的体硅CMOS处理技术制造器件。 优点包括单芯片架构，卓越的高频性能，低功耗和成本有效的制造。

公开(公告)号：EP2624451B1

公开(公告)日：2017-06-07

申请号：EP11829169.9

申请日：2011-09-28

申请人： Murata Manufacturing Co., Ltd.

发明人： ITO, Korekiyo

IPC分类号： H03H9/25 ,  H03H3/02 ,  H03H3/08 ,  H03H9/17 ,  H01L41/08 ,  H01L41/312 ,  H03H9/05 ,  H03H9/02

CPC分类号： H01L41/253 ,  H01L21/02694 ,  H01L41/0536 ,  H01L41/081 ,  H01L41/0815 ,  H01L41/0838 ,  H01L41/18 ,  H01L41/27 ,  H01L41/277 ,  H01L41/297 ,  H01L41/312 ,  H01L41/332 ,  H01L41/47 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02574 ,  H03H9/059 ,  H03H9/173

摘要： Disclosed is a piezoelectric device free of some problems associated with ion implantation: the degradation of the surface roughness of the piezoelectric thin film and the cracking of the supporting substrate. Also disclosed is a method for manufacturing this piezoelectric device. During an isolation formation step a supporting substrate (50) has a piezoelectric thin film (10) formed on its front (14) with a compressive stress film (90) present on its back (15). The compressive stress film (90) compresses the surface (14 on the piezoelectric single crystal substrate (1) side of the supporting substrate (50), and the piezoelectric thin film (10) compresses the back (15) of the supporting substrate (50), which is opposite to the surface (14) on the piezoelectric single crystal substrate (1) side. In other words, the compressive stress produced by the compressive stress film (90) and that by the piezoelectric thin film (10) are in balance in the supporting substrate (50). This makes the supporting substrate (50) free of warpage and able to remain flat. To this end, the driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film (10).

摘要翻译： 公开了一种没有与离子注入相关的问题的压电器件：压电薄膜的表面粗糙度的降低和支撑衬底的破裂。 还公开了用于制造该压电器件的方法。 在隔离形成步骤期间，支撑衬底（50）具有在其前部（15）上形成有压缩应力膜（90）的压电薄膜（10）。 压缩应力膜（90）压缩支撑基板（50）的压电单晶基板（1）侧的表面（14），压电薄膜（10）压缩支撑基板（50）的背面（15） ）与压电单晶基板（1）一侧的表面（14）相对，换句话说，由压应力膜（90）产生的压应力和由压电薄膜（10）产生的压应力处于 在支撑基板50上形成平衡，因此支撑基板50不会发生翘曲而能够保持平坦，因此在隔离形成工序中引起隔离的驱动力是被注入的离子化元件的气化，而不是 由压电薄膜（10）产生的对隔离平面的压缩应力。

公开(公告)号：EP3142152A1

公开(公告)日：2017-03-15

申请号：EP16188202.2

申请日：2016-09-09

申请人： Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS

发明人： AUGENDRE, Emmanuel ,  HALIMAOUI, Aomar ,  MAITREJEAN, Sylvain ,  REBOH, Shay

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02694 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78687

摘要： Procédé de réalisation d'une couche de matériau semi-conducteur comprenant des étapes de :
a) formation d'un empilement comprenant une première couche (3) à base d'un premier matériau semi-conducteur revêtu d'une deuxième couche (6) à base d'un deuxième matériau semi-conducteur de paramètre de maille différent de celui du premier matériau semi-conducteur,
b) réaliser sur la deuxième couche semi-conductrice un masque (10) présentant une symétrie,
c) rendre amorphe la première couche semi-conductrice (3) ainsi que des zones (6') de la deuxième couche semi-conductrice (6) sans rendre amorphe une ou plusieurs régions (6a, 6b, 6c) de la deuxième couche semi-conductrice protégées par le masque et disposées respectivement en regard du ou des blocs de masquage
d) effectuer une recristallisation des régions rendues amorphes (6a, 6b, 6c) et de la première couche semi-conductrice d'où il résulte que cette première couche semi-conductrice est contrainte.