公开(公告)号：EP0532542A1

公开(公告)日：1993-03-24

申请号：EP91909894.0

申请日：1991-02-06

申请人： CRAY RESEARCH, INC.

发明人： LEEDOM, George, W. ,  SCHIFFLEGER, Alan, J. ,  GUPTA, Ram, K.

IPC分类号： G06F15

CPC分类号： G06F15/173

摘要： Procédé et appareil de partage de mémoire (12) dans un système à processeurs multiples (10) comprenant une pluralité de processeurs (0-15) qui comporte chacun une pluralité de points d'accès pour produire des références de mémoire, la mémoire étant divisée en une pluralité de sections, (0-7) chaque section étant connectée à chaque processeur par une voie d'accès à la mémoire (14). Lesdites sections comprennent une pluralité de sous-sections de mémoire, chacune d'entre elles comportant une pluralité de groupes de mémoires comportant chacun une pluralité de blocs de mémoire. Lesdits blocs de mémoire sont connectés aux voies d'accès à la mémoire si bien que les processeurs peuvent consulter la mémoire partagée par l'intermédiaire des points d'accès à la mémoire. Chaque voie d'accès est connectée à chaque section par une interface processeur-section pour chaque unité centrale qui reçoit des références d'un processeur associé et adresse lesdites références aux sous-sections dans la section. Un circuit d'interface de groupe pour chaque groupe comprend une pluralité de bascules, une pour chaque processeur, destinées à recevoir des références pour le groupe à partir de son processeur associé. Les références sont ventilées vers des bascules correspondantes dans les groupes de chaque sous-section. Dans chaque groupe, un circuit de références au niveau du groupe transmet les références détenues dans les bascules aux blocs de la mémoire. Une voie d'accès aux données permet l'entrée et la sortie des données de chaque section en direction et à partir de chaque processeur.

公开(公告)号：EP0494862A1

公开(公告)日：1992-07-22

申请号：EP90907635.0

申请日：1990-05-09

申请人： CRAY RESEARCH, INC.

发明人： FROMM, Eric, C. ,  HEIDTKE, Lonnie, R.

IPC分类号： G06F12 ,  G11C7 ,  G11C11

CPC分类号： G11C7/1033 ,  G11C7/1039

摘要： La mémoire RAM dynamique décrite est organisée en une pluralité de sections renfermant chacune une pluralité de groupes, contenant chacun une pluralité de rangs de puces mémoires DRAM. Un chemin de données pipeline est prévu à l'intérieur et en dehors de chaque groupe, et l'accès en mode quartet est facilité par un traitement pipeline simultané des données à l'intérieur et à l'extérieur de la mémoire tandis que s'effectuent les opérations de consultation de la mémoire.

公开(公告)号：EP0389001A3

公开(公告)日：1991-12-04

申请号：EP90109463.1

申请日：1984-04-18

申请人： CRAY RESEARCH, INC.

发明人： Chen, Steve S. ,  Schiffleger, Alan J. ,  Somdahl, Eugene R. ,  Higbie, Lee

IPC分类号： G06F15/16 ,  G06F15/78

CPC分类号： G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3879 ,  G06F13/18 ,  G06F15/17 ,  G06F15/8092

摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between the CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devi­ces. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multi­tasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and faciliates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.

公开(公告)号：EP0419499A1

公开(公告)日：1991-04-03

申请号：EP89905827.0

申请日：1989-04-07

申请人： Cray Research, Inc.

发明人： CRAY, Seymour, R. ,  BEDELL, James, Richard ,  KUBA, Dennis, W. ,  MOORE, William, T., Jr.

IPC分类号： G06F17 ,  G06F9 ,  G06F15

CPC分类号： G06F15/8076

摘要： On obtient des performances améliorées dans des ordinateurs du type possédant des registres vectoriels qui communiquent avec une ou plusieurs unités fonctionnelles et une mémoire commune. A mesure que des éléments d'un vecteur sont lus dans un registre vectoriel à des fins de transmission à une mémoire commune ou bien sous forme d'opérandes à une unité fonctionnelle, le registre vectoriel devient immédiatement disponible pour recevoir et stocker des éléments d'un vecteur émanant de la mémoire commune ou d'une unité fonctionnelle. Le stockage élément par élément se produit simultanément avec la lecture élément par élément, et suit la lecture avec un décalage d'au moins un élément de manière à ne pas recouvrir des éléments restant à lire. La mise en oeuvre de cette technique permet de charger un registre vectoriel avec un vecteur destiné à une opération subséquente sans avoir à attendre l'achèvement de l'opération précédente qui fait intervenir le même registre vectoriel.

公开(公告)号：EP0276641A3

公开(公告)日：1990-03-28

申请号：EP87850323.4

申请日：1987-10-28

申请人： Cray Research, Inc.

发明人： Fromm, Eric C.

IPC分类号： H04L25/48

CPC分类号： H04L25/4902

摘要： A data modulation interface is provided for serial data transmission. A biphase signal is encoded with the binary bits of a parallel data word. The bits of the parallel data word are examined to determine whether there are more one bits or zero bits in the word. A polarity bit is provided in addition to the other bits to indicate which bit-state occurred most often. The biphase signal is modulated to create dif­ferent time intervals between phase reversals with one time interval corresponding to a bit-state of one and another time interval corresponding to a bit-state of zero. The shortest time interval is assigned to correspond to the bit-state occurring most often in the word so that the total time required to transmit each word is minimized. A time interval can be assigned to a sync signal transmitted after each parallel data word. A time interval can also be assigned to correspond to plural bit combinations so they can be represented by a single phase interval and transmitted quickly.

公开(公告)号：EP0263585A3

公开(公告)日：1990-01-03

申请号：EP87307342.3

申请日：1987-08-19

申请人： CRAY RESEARCH, INC.

发明人： August, Melvin C. ,  Bowen Stephen A. ,  Williams, John T.

IPC分类号： H01R23/70 ,  H01R13/193

CPC分类号： H01R13/193

摘要： An electrical edge connector (14) of the zero insertion force type includes a pair of opposing blocks (30, 32) defining a longitudinal guideway (34) therebet­ween. Opposite corresponding pairs of female contacts (52, 54) are disposed in transverse holes in the blocks (30, 32), and male contacts (60) are slidably supported in the female contacts in one block for selective actuation into or out of sliding engagement with the female contacts in the other block responsive to inser­tion of a slider (36).

公开(公告)号：EP0129966B1

公开(公告)日：1988-03-02

申请号：EP84302756.6

申请日：1984-04-24

申请人： Cray Research, Inc.

发明人： August, Melvin C. ,  Williams, John T.

IPC分类号： H01L23/36 ,  H05K7/20

CPC分类号： H05K1/0206 ,  H01L23/36 ,  H01L2924/0002 ,  H05K3/341 ,  H05K3/429 ,  H05K2201/09054 ,  H05K2201/09572 ,  H05K2201/10416 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00

公开(公告)号：EP0123509A2

公开(公告)日：1984-10-31

申请号：EP84302632.9

申请日：1984-04-18

申请人： Cray Research, Inc.

发明人： Chen, Steve S. ,  Schiffleger, Alan J. ,  Somdahl, Eugene R. ,  Higbie, Lee

IPC分类号： G06F15/16 ,  G06F15/347

CPC分类号： G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3879 ,  G06F13/18 ,  G06F15/17 ,  G06F15/8092

摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one t/0 port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.

摘要翻译： 两个处理器（10,11）中的每一个具有到中央存储器（12）的数据（13,14）和控制路径（15,16）。 相应的控制路径（21,22）将每个处理器连接到通过双向数据路径（23）连接到存储器的CPU输入输出控制（20）。 存储器被布置在交织的存储体中，用于在每个机器时钟周期期间进行独立的并行访问。 处理器之间的相互通信是通过具有在处理器的共同控制下的共享寄存器的通信和控制电路（50），并且可以通过相应数据路径（51,52）从任一个CPU读取或写入。 数据传输通过电路（50）寄存器或中央存储器由信号量寄存器进行协调。

公开(公告)号：EP1038375A1

公开(公告)日：2000-09-27

申请号：EP98963942.2

申请日：1998-12-16

申请人： CRAY RESEARCH, INC.

发明人： PRIBNOW, Richard, D. ,  BYE, Michael, T. ,  BRAVATTO, James, G. ,  KLINE, John, Theodore

IPC分类号： H04L12/42 ,  G06F15/17 ,  G06F15/173

CPC分类号： H04L47/10 ,  H04L12/42

摘要： A ring computer network system having a communication controller for controlling the receipt and sending of packets or messages at each client computer. The interface associated with each client computer includes a send message buffer and a receive message buffer. The send message buffer has a send message buffer counter which increments upwardly is response to messages being received from the client computer for sending on the ring network. The communication controller sends messages from the send buffer until the send message buffer counter reaches the address or a value associated with the last received message. Similarly, the receive message buffer includes a receive message buffer counter which increments as each message is received to a receive message buffer counter value. The receive message buffer is emptied until the receive message buffer counter value is reached. The receive buffer can also have a foreground portion and a background portion. The send buffer can also have a background portion and a foreground portion of memory. The communication controller continually switches between the foreground and background portions of memory and redesignates each memory portion after the switch. The communications controller can also recognize priority schemes for the messages.

公开(公告)号：EP1032887A1

公开(公告)日：2000-09-06

申请号：EP98959468.4

申请日：1998-11-16

申请人： CRAY RESEARCH, INC.

发明人： PASSINT, Randal, S. ,  GALLES, Michael, B. ,  THORSON, Greg

IPC分类号： G06F15/173

CPC分类号： G06F15/17381

摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communications links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.