公开(公告)号：EP1741671B1

公开(公告)日：2010-09-15

申请号：EP05425488.3

申请日：2005-07-08

申请人： STMicroelectronics Srl

发明人： Mascolo, Danilo ,  Cerofolini, Gianfranco

IPC分类号： H01L21/768 ,  G11C13/02

CPC分类号： H01L21/76838 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C2213/81 ,  H01L21/76816 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1793274A3

公开(公告)日：2009-09-23

申请号：EP06003781.9

申请日：2006-02-24

申请人： FUJITSU LIMITED

发明人： Kozawa, Miwa, c/o FUJITSU LIMITED ,  Nozaki, Koji, c/o FUJITSU LIMITED

IPC分类号： G03F7/00 ,  G03F7/40 ,  H01L21/027

CPC分类号： G03F7/40 ,  H01L21/0273 ,  H01L21/76816

摘要： The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. The present invention also provides a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.

公开(公告)号：EP1946355A1

公开(公告)日：2008-07-23

申请号：EP06778031.2

申请日：2006-07-27

申请人： International Business Machines Corporation

发明人： HICHRI, Habib ,  LARSEN, Kimberly ,  MAYNARD, Helen c/o IBM U.K. Limited I.P.L. ,  PETRARCA, Kevin

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01F17/00

CPC分类号： H01L21/02118 ,  H01F41/041 ,  H01L21/02282 ,  H01L21/3083 ,  H01L21/312 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

公开(公告)号：EP1764830A2

公开(公告)日：2007-03-21

申请号：EP05447238.6

申请日：2005-10-21

申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

发明人： Beyer, Gerald

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

摘要： The present invention relates to a method for the production of very small trenches in semiconductor devices.
The formation of these small trenches is based on chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in said first dielectric layer are converted locally and become etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.
The small trenches obtained by chemically changing the properties of a dielectric layer can be used as test vehicle to study barrier deposition, copper plating and seedlayer deposition within very small trenches (order 10-30 nm).

摘要翻译： 本发明涉及在半导体器件中制造非常小的沟槽的方法。 这些小沟槽的形成是基于局部化学地改变第一介电层的性质，使得所述第一介电层中的图案化孔的侧壁被局部转化并且可被第一蚀刻物质蚀刻。 随后，在图案化结构中沉积第二介电材料，并且去除第一介电材料的损坏部分，从而获得小的沟槽。 通过化学改变电介质层的性质获得的小沟槽可以用作测试载体，以研究在非常小的沟槽（10-30nm）内的阻挡层沉积，铜电镀和种子层沉积。

公开(公告)号：EP1761949A2

公开(公告)日：2007-03-14

申请号：EP05752268.2

申请日：2005-05-19

申请人： MOLECULAR IMPRINTS, INC.

发明人： SREENIVASAN, Sidlgata, V.

IPC分类号： H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/3086 ,  H01L21/76816 ,  H01L21/76817

摘要： The present invention provides a method of forming recesses on a substrate, the method including forming on the substrate a patterning layer having first features; trim etching the first features to define trimmed features having a shape; and transferring an inverse of the shape into the substrate.

公开(公告)号：EP1733420A2

公开(公告)日：2006-12-20

申请号：EP05730266.3

申请日：2005-03-23

申请人： MICRON TECHNOLOGY, INC.

发明人： SINHA, Nishant ,  CHOPRA, Dinesh ,  FISHBURN, Fred, D.

IPC分类号： H01L21/288 ,  H01L21/768

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure (102) thereover with a surface suitable for electroless plating, and to also have a digit line (54) thereover having about the same height as the dummy structure. A layer (56) can be formed over the dummy structure and digit line, and openings (120, 122) can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening (122) extending to the dummy structure can pass through a capacitor electrode (62), and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

公开(公告)号：EP1532679A2

公开(公告)日：2005-05-25

申请号：EP03793383.5

申请日：2003-08-21

申请人： INTEL CORPORATION

发明人： BOHR, Mark

IPC分类号： H01L21/768

CPC分类号： H01L21/76816 ,  Y10S257/903

摘要： The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but now down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory and various other memory cells.

公开(公告)号：EP1378002A2

公开(公告)日：2004-01-07

申请号：EP02718080.1

申请日：2002-01-16

申请人： International Business Machines Corporation ,  Infineon Technologies North America Corp. ,  Compagnie IBM France

发明人： ARMACOST, Michael, D. ,  AUGUSTIN, Andreas, K. ,  FRIESE, Gerald, R. ,  HEIDENREICH, John, E., III ,  HUECKEL, Gary, R. ,  STEIN, Kenneth, J.

IPC分类号： H01L21/02

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3ν) with a bottom etch stop layer (104), a composite bottom plate (110) having an aluminium layer below a TiN layer, an oxide capacitor dielectric (120), and a top plate (130) of TiN. The process involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：EP0961311A3

公开(公告)日：2003-03-05

申请号：EP99110230.2

申请日：1999-05-26

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tanaka, Keisuke ,  Nagano, Yoshihisa ,  Ito, Toyoji ,  Mikawa, Takumi

IPC分类号： H01L21/02 ,  H01L21/285

CPC分类号： H01L28/55 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/76816

摘要： A capacitor includes lower electrode, capacitive insulating film, upper electrode and passivation film that are formed in this order on a substrate. The capacitive insulating film is made of an insulating metal oxide, the metal oxide being a ferroelectric or a dielectric with a high relative dielectric constant. At least one contact hole is formed in the passivation film to connect the lower electrode to an interconnect for the lower electrode or the upper electrode to an interconnect for the upper electrode. The opening area of the contact hole is equal to or smaller than 5µm 2 .

摘要翻译： 电容器包括在基板上依次形成的下电极，电容绝缘膜，上电极和钝化膜。 电容绝缘膜由绝缘金属氧化物制成，金属氧化物是铁电体或具有高相对介电常数的电介质。 在钝化膜中形成至少一个接触孔，以将下电极与下电极或上电极的互连连接成上电极的互连。 接触孔的开口面积等于或小于5微米2。

公开(公告)号：EP0895656B1

公开(公告)日：2002-05-08

申请号：EP97903893.2

申请日：1997-02-04

申请人： ADVANCED MICRO DEVICES INC.

发明人： STOLMEIJER, Andre

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L21/027

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

摘要： The present invention provides a method for fabricating small structures to be employed in integrated circuits formed on a semiconductor substrate (12). Examples of such small structures include contacts, vias, and metal lines. The method of the present invention employs an image reversal technique to obtain improved feature definition. In forming a feature (28) in a layer of material (16), a clear field reticle is used to form patterned segments of photoresist (18) each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). This method is employed instead of using a dark field reticle which forms windows in a photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features (28) intended to be formed in the layer of material (16). For small structures, the openings or windows in a photoresist are harder to form than the patterned segments of photoresist (18). With the method of the present invention which employs a clear field reticle to form a mask comprising patterned segments of photoresist (18), the limitations of patterning small windows in a photoresist with the use of a dark field reticle are avoided. The accuracy of forming the small structures is thus improved.