Method and apparatus for image communication
    73.
    发明公开
    Method and apparatus for image communication 失效
    Verfahren und VorrichtungfürBildkommunikation

    公开(公告)号:EP0768798A2

    公开(公告)日:1997-04-16

    申请号:EP96116091.8

    申请日:1996-10-08

    申请人: FUJITSU LIMITED

    IPC分类号: H04N7/24

    摘要: It is disclosed a transmission apparatus for a fixed length cell handling image communication method wherein moving picture data are compressed to data having a fixed transmission rate using a compression method for still pictures and then converted into fixed length cells so that image processing such as compression/decompression of the moving picture data can be performed at a high rate while keeping a high compression ratio and a high picture quality. Said apparatus includes an image data compression section (3) for performing still picture compression processing for moving picture data, which define information of a plurality of screens individually divided into a plurality of fields to be successively transmitted per unit time, in response to field timing information representative of a compression timing of each field to convert the moving picture data into variable length data which are independent of each other, a transmission buffer section (4) for converting the variable length data into fixed length data having a fixed transmission rate, and a fixed length cell transmission section (5) for placing the fixed length data and the field timing information into data parts of fixed length cells and transmitting the fixed length cells.

    摘要翻译: 公开了一种固定长度单元处理图像通信方法的发送装置,其中使用静态图像的压缩方法将运动图像数据压缩为具有固定传输速率的数据,然后转换成固定长度的单元,使得诸如压缩/ 可以以高速率执行运动图像数据的解压缩,同时保持高压缩比和高图像质量。 所述装置包括图像数据压缩部分(3),用于响应于场定时,对每个单位时间内分别划分为要连续发送的多个场的多个屏幕的信息进行运动图像数据的静止图像压缩处理 用于将运动图像数据转换成彼此独立的可变长度数据的每个场的压缩定时的信息;用于将可变长度数据转换成具有固定传输速率的固定长度数据的传输缓冲器部分(4),以及 用于将固定长度数据和场定时信息放入固定长度单元的数据部分并发送固定长度单元的固定长度单元传输部分(5)。

    Method and apparatus for adaptive clock recovery
    74.
    发明公开
    Method and apparatus for adaptive clock recovery 失效
    自适应时钟恢复的方法和装置。

    公开(公告)号:EP0622918A3

    公开(公告)日:1996-04-17

    申请号:EP94302590.8

    申请日:1994-04-13

    申请人: AT&T Corp.

    IPC分类号: H04J3/06 H04L7/02 H04Q11/04

    摘要: An adaptive clock recovery arrangement for deriving a synchronous clock from an asynchronous, packet stream (11) such as an asynchronous transfer mode (ATM) cell stream. The deviation in the magnitude of information stored in a first-in-first-out memory (15) is continually monitored (25), and the synchronous clock frequency, referred to as the adaptive line clock frequency, is adjusted in a plurality of modes, under the control of a processor (29). The adjustment is made in response to a detected increasing condition of the monitored deviation. The adjustments are open-loop adjustments made without continually adjusting the adaptive line clock frequency based on the monitored deviation. Damping is substantially reduced compared with "conventional" PLL arrangements because the open-loop adjustments result in a rapid frequency correction with perfect or nearly perfect deadbeat damping, i.e. without the frequency oscillations that continue after the correct frequency is reached in closed-loop arrangements.

    Method and apparatus for adaptive clock recovery
    76.
    发明公开
    Method and apparatus for adaptive clock recovery 失效
    Verfahren und Vorrichtung zur adaptivenTaktrückgewinnung。

    公开(公告)号:EP0622918A2

    公开(公告)日:1994-11-02

    申请号:EP94302590.8

    申请日:1994-04-13

    申请人: AT&T Corp.

    IPC分类号: H04J3/06 H04L7/02 H04Q11/04

    摘要: An adaptive clock recovery arrangement for deriving a synchronous clock from an asynchronous, packet stream (11) such as an asynchronous transfer mode (ATM) cell stream. The deviation in the magnitude of information stored in a first-in-first-out memory (15) is continually monitored (25), and the synchronous clock frequency, referred to as the adaptive line clock frequency, is adjusted in a plurality of modes, under the control of a processor (29). The adjustment is made in response to a detected increasing condition of the monitored deviation. The adjustments are open-loop adjustments made without continually adjusting the adaptive line clock frequency based on the monitored deviation. Damping is substantially reduced compared with "conventional" PLL arrangements because the open-loop adjustments result in a rapid frequency correction with perfect or nearly perfect deadbeat damping, i.e. without the frequency oscillations that continue after the correct frequency is reached in closed-loop arrangements.

    摘要翻译: 一种自适应时钟恢复装置,用于从诸如异步传输模式(ATM)小区流的异步分组流(11)导出同步时钟。 持续地监视存储在先进先出存储器(15)中的信息的幅度的偏差(25),并且称为自适应线路时钟频率的同步时钟频率以多种模式 在处理器(29)的控制下。 响应于检测到的监视偏差的增加状况进行调整。 调整是开环调整,而不是根据监测的偏差不断调整自适应线路时钟频率。 与“常规”PLL布置相比,阻尼显着降低,因为开环调节导致快速频率校正,具有完美或接近完美的无节拍阻尼,即,在闭环布置中达到正确频率之后没有频率振荡继续。

    Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks
    77.
    发明公开
    Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks 失效
    TaktwiedergewinnungfürVideo mit variabler Bite-Rate inAsynchronübertragungsnetzwerken。

    公开(公告)号:EP0577329A2

    公开(公告)日:1994-01-05

    申请号:EP93304927.2

    申请日:1993-06-24

    申请人: AT&T Corp.

    IPC分类号: H04N7/13

    摘要: Complications of timing recovery in an ATM receiver (200) are overcome by employing a first phase lock loop (208) including a phase comparator (210), filter (211), voltage controlled oscillator (212) and output counter (214) to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter (214) is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then. so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. Underflow of the receiver data buffers (202,205) is alleviated by the addition of a "jitter-delay (D j )" value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained (217) by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The stability of the video decoder (204) timing is enhanced by employing an additional phase locked loop in a video display control (203) which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frquency in which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.

    摘要翻译: 通过采用包括相位比较器(210),滤波器(211),压控振荡器(212)和输出计数器(214)的第一锁相环(208)来克服ATM接收器(200)中的定时恢复的并发症,以锁定 到从远程ATM发射机异步接收的系统时钟参考(SCR)值。 SCR值表示异步SCR值传输时刻的系统定时时钟(STC)的瞬时值。 在接收机中,首先将输出计数器(214)设置为初始接收到的SCR值的值,使得导出的STC可用于解码初始接收分组中的数据单元。 然后。 包括在音频和视频数据中的所谓的显示/解码时间戳(PTS / DTS)有利地与STC一起使用以正确地显示所接收的数据。 通过添加“抖动延迟(Dj)”值来减轻接收器数据缓冲器(202,205)的下溢,这在解码之前在数据缓冲器中引起数据的额外累加。 通过监视数据缓冲区的丰满度和可控地调整抖动延迟,获得通道的抖动延迟的动态跟踪(217)。 通过在被提供有定时误差信号的视频显示控制(203)中采用附加锁相环来增强视频解码器(204)定时的稳定性。 附加锁相环包括开关,滤波器,限幅器和压控振荡器(VCO)。 响应于来自VCO的输出脉冲启用该开关以向每个所谓的视频呈现单元向滤波器提供输入的瞬时误差信号。 VCO具有非常稳定的中心频率,其中通过将输入控制电压钳位到一些小的电压范围来限制变化。 来自VCO的输出脉冲用于使得能够对演示单元进行解码。 通过增加压控器的允许电压范围,可以在起动时提供更快的同步。