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232 条记录 (耗时 0.021 秒)

    A semiconductor memory device of a dynamic type having a data read/write circuit
    81.
    发明公开
    A semiconductor memory device of a dynamic type having a data read/write circuit 失效
    具有数据读/写电路的动态类型的半导体存储器件

    公开(公告)号：EP0037239A3

    公开(公告)日：1983-06-29

    申请号：EP81301269

    申请日：1981-03-25

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C07/00 ,  G11C11/24

    CPC分类号： G11C5/066 ,  G11C11/4093

    摘要： The read/write circuit comprises a data output buffer (DOB) connected through a three-state circuit (Qa, Q b ) to a common data input/output terminal (I/O), and a data write-in buffer (DWB) of a dynamic type having a latching function connected between the common data input/output terminal (I/O) and data buses (DB, DB) for providng latched data to the data buses. By utilizing a rise or a fall of a write enable signal (WE) or a column address strobe signal (CAS) applied to the memory device, the three-state circuit (Qa, Q b ) is set to a high impedance state, and then write data is latched into the data write-in buffer (DWB).

    Dynamic random access memory device
    82.
    发明公开
    Dynamic random access memory device 失效
    Dynamische Direktzugriffspeicheranordnung。

    公开(公告)号：EP0068894A2

    公开(公告)日：1983-01-05

    申请号：EP82303414.5

    申请日：1982-06-29

    申请人： FUJITSU LIMITED

    发明人： Nakano, Tomio ,  Nakano, Masao ,  Takemae, Yoshihiro ,  Tsuge, Norihisa ,  Ohira, Tsuyoshi

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4099 ,  G06F11/2294

    摘要： A dynamic random access memory device comprises one-transistor, one-capacitor-type memory cells (Coo - C 127.127 ) in rows and columns and dummy cells (DC20'~ DC 2,127 , DC 20 " ~ DC 2.127 ", DC20'" ~ DC 2,127 "') in rows. The capacitors (C d ) of the dummy cells are charged to a high power supply potential (V cc ) by one or more charging transistors (Q A , QA') clocked by a reset clock signal (0R). The capacitors (C d ) of the dummy cells are discharged to a low power supply potential (V ss ) by one or more transistors (Q B , Q B ') clocked by an operation clock signal (⌀ WL ) having a potential lower than the high power supply potential (V cc ).

    摘要翻译： 动态随机存取存储器件包括行和列中的单晶体管，单电容器型存储单元（C00 SIMILAR C127,127）和虚拟单元（DC20分钟，类似DC2,127，DC20秒，类似DC2,127秒，DC20' “”SIMILAR DC2,127“”）。 虚拟单元的电容器（Cd）通过由复位时钟信号（0R）定时的一个或多个充电晶体管（QA，QA min）充电到高电源电位（VCC）。 虚拟单元的电容器（Cd）由一个或多个晶体管（QB，QB min）放电到低电源电位（VSS），由具有低于高电源电位的电位的操作时钟信号（0WL） （VCC）。

    Inverter circuit
    83.
    发明公开
    Inverter circuit 失效
    Inverterschaltung。

    公开(公告)号：EP0068892A2

    公开(公告)日：1983-01-05

    申请号：EP82303412.9

    申请日：1982-06-29

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C8/00 ,  H03K19/017

    CPC分类号： H03K3/3565 ,  G11C8/08 ,  G11C8/18 ,  H03K19/01714

    摘要： An inverter circuit comprises a load transistor (Q 1 ) and a driving transistor (Q 2 ) connected in series between power supplies (V ss , Vpp). At least one transistor (Q 3 ) for reducing the load of the load transistor is connected between the load transistor and the power supply (Vpp). A bootstrap circuit is connected to the gate of the transistor (Q 3 ) and the gate potential of the transistor (Q 3 ) is risen up to a potential level higher than the power supply (Vpp).

    Integrated semiconductor device including a Bias voltage generator
    84.
    发明公开
    Integrated semiconductor device including a Bias voltage generator 失效
    Integrierte Halbleiterschaltung mit Vorspannungserzeuger。

    公开(公告)号：EP0067688A1

    公开(公告)日：1982-12-22

    申请号：EP82303044.0

    申请日：1982-06-11

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Nakano, Masao ,  Tsuge, Norishisa ,  Ohira, Tsuyoshi

    IPC分类号： G05F3/20

    CPC分类号： G05F3/205

    摘要： An IC semiconductor device includes a bias-voltage generator comprising an oscillator (OSC), a charge-pumping circuit which is driven by the oscillator via a pumping capacitator, and a charge-pumping switch (41). The charge-pumping switch (41) is connected in series with the charge-pumping circuit. The charge-pumping switch is operated by an external electrode (PAD). The charge-pumping switch is turned OFF by the external electrode substrate leak circuit when measurement of substrate leak current is to be carried out, thereby enabling greater accuracy of measurement.

    摘要翻译： IC半导体器件包括偏置电压发生器，其包括振荡器（OSC），经由泵浦电容器由振荡器驱动的电荷泵浦电路和电荷泵浦开关（41）。 电荷泵浦开关（41）与电荷泵浦电路串联连接。 电荷泵开关由外部电极（PAD）操作。 当要进行基板泄漏电流的测量时，电荷泵浦开关由外部电极基板泄漏电路断开，从而能够实现更高的测量精度。

    Semiconductor circuit for driving clock signal line
    86.
    发明公开
    Semiconductor circuit for driving clock signal line 失效
    半导体电路，用于控制时钟信号线。

    公开(公告)号：EP0058509A2

    公开(公告)日：1982-08-25

    申请号：EP82300645.7

    申请日：1982-02-09

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nozaki, Shigeki ,  Kabashima, Katsuhiko ,  Enomoto, Seiji

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4085 ,  G11C11/4076 ,  H03K5/023

    摘要： A semiconductor circuit for driving a clock signal line comprising a first circuit for pulling up the potential of the clock signal line to the source voltage, a second circuit for pulling down the potential of the clock signal line to a lower voltage, and a capacitor connected to the clock signal line for receiving a potential push signal and pushing the potential of the clock signal line up to higher than the source voltage, the capacitor being able to perform the function of capacitance only after the potential of the clock signal line is raised to the source voltage, whereby the operational speed of a dynamic memory device associated with the semiconductor device is enhanced.

    Semiconductor memory device with substrate voltage biasing
    88.
    发明公开
    Semiconductor memory device with substrate voltage biasing 无效
    具有基极电压偏置的半导体存储器件

    公开(公告)号：EP0036246A3

    公开(公告)日：1981-09-30

    申请号：EP81300597

    申请日：1981-02-13

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Baba, Fumio

    IPC分类号： G11C11/24 ,  G05F03/20 ,  G11C07/00

    CPC分类号： G11C7/00 ,  G05F3/205 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091

    摘要： A semiconductor memory device comprises a sense amplifier (1) formed on a semiconductor substrate (10), paired bit lines (BL) connected to the sense amplifier and memory cells (MC) connected to the bit lines. A predetermined bias voltage is applied to the semi-conductor substrate, and a reading operation is performed by amplifying, by means of the sense amplifier, a voltage difference produced between the paired bit lines due to accessing the memory cells. A voltage of reverse phase relative to noise on the bias voltage applied to the substrate is fed to the semiconductor substrate via a capacitance (21 formed on the substrate, to cancel the noise. By virtue of this feature, the influence of such noise can be minimised in the semiconductor memory device of the present invention.