中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

87 records (took 0.018 seconds)

    Topology for providing clock signals to multiple circuit units on a circuit module
    81.
    发明公开
    Topology for providing clock signals to multiple circuit units on a circuit module 有权
    Topologie zurVerfügungstellungvon Taktsignalen a mehrere Schaltungseinheiten auf einem Schaltungsmodul

    公开(公告)号：EP1457861A1

    公开(公告)日：2004-09-15

    申请号：EP03005541.2

    申请日：2003-03-11

    Applicant: Infineon Technologies AG

    Inventor： Kuzmenka, Maksim ,  Chennupati, Siva RaghuRam ,  Bacha, Abdallah ,  Muff, Simon

    IPC: G06F1/10

    CPC classification number: G11C7/1066 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/1506 ,  H03L7/06 ,  H03L7/07 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

    Abstract: A circuit module has a circuit board (50a), multiple circuit units (20a to 52i) on the circuit board (50a) and at least one clock input (12a) on the circuit board (50a) for receiving an external clock signal. The circuit module has a first PLL unit (60) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit (62) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.

    Abstract translation: 电路模块具有电路板（50a），电路板（50a）上的多个电路单元（20a至52i）和电路板（50a）上的至少一个时钟输入（12a），用于接收外部时钟信号。 电路模块具有在电路板（50a）上的第一PLL单元（60），用于基于外部时钟信号向至少第一个电路单元提供内部时钟信号。 此外，电路模块在电路板（50a）上具有第二PLL单元（62），用于基于外部时钟信号向至少第二电路单元提供内部时钟信号。

    BACKPLANE FOR HIGH SPEED DATA PROCESSING SYSTEM
    82.
    发明公开
    BACKPLANE FOR HIGH SPEED DATA PROCESSING SYSTEM 失效
    BACK FOR HIGH-SPEED数据处理系统

    公开(公告)号：EP0958717A4

    公开(公告)日：2002-07-24

    申请号：EP97920374

    申请日：1997-04-11

    Applicant: ARIZONA DIGITAL INC

    Inventor： BERDING ANDREW R

    IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14

    CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09263

    Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. In one embodiment of the invention, a set of common points (23, 24) is electrically coupled to the connectors by individual conductive traces between each common point (23) and the corresponding pins (31-36) of the connectors. The common points are preferably centrally located among the plurality of connectors to reduce propagation delay. A connector (75) can be attached at the common points. The traces are separated from each other by lateral displacement in a single plane. If the backplane is a multi-layered printed circuit board, the traces are separated from each other by vertical displacement between the layers of the printed circuit board or by both vertical and horizontal displacement. The traces to the connectors nearest the common points (83) have a minimum length (96) greater than the distance (92) between the nearest connectors and the common points.

    BAUGRUPPENTRÄGER FÜR EIN ELEKTRONISCHES STEUERGERÄT MIT SIGNALVERARBEITENDEN BAUELEMENTEN UND SCHNELL ARBEITENDEN DIGITALEN BAUELEMENTEN
    84.
    发明公开
    BAUGRUPPENTRÄGER FÜR EIN ELEKTRONISCHES STEUERGERÄT MIT SIGNALVERARBEITENDEN BAUELEMENTEN UND SCHNELL ARBEITENDEN DIGITALEN BAUELEMENTEN 失效
    模块的面板与信号处理元件和快速的数码元件电子控制单元

    公开(公告)号：EP0801884A1

    公开(公告)日：1997-10-22

    申请号：EP96924758.0

    申请日：1996-07-20

    Applicant: ROBERT BOSCH GMBH

    Inventor： ROOZENBEEK, Herman ,  TEPASS, Bernd

    IPC: H05K9 ,  H05K1

    CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09972 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: The invention concerns a module mounting rack for an electronic control unit with signal-processing analogue and/or digital components, rapid-operation digital components and components with both signal-processing functional parts and rapid-operation digital functional parts and power components which are disposed on a multilayer printed circuit board and are connected in an electrically conductive manner to a common earth layer. The signal-processing components of each module are jointly connected to the common earth layer. The noise radiation of the control unit, caused by high-frequency interference current, can be reduced and impairment of signal processing by high current densities in the earth layer and resultant potential shifts can be prevented by combining the signal-processing components to form signal-processing modules having at least one common function, and guiding the earth connections of all the components of each such functional module via line connections to a common connection point which is conductively connected in the shortest possible way to the common earth layer. The rapid-operation digital and power components are directly connected to the common earth layer. By introducing an additional power supply layer, the noise radiation of the control unit can be reduced even further.

    Signal routing technique for high frequency electronic systems
    86.
    发明公开
    Signal routing technique for high frequency electronic systems 失效
    Signalleittechnikfürhochfrequente elektronische Systeme。

    公开(公告)号：EP0519740A2

    公开(公告)日：1992-12-23

    申请号：EP92305658.4

    申请日：1992-06-19

    Applicant: Compaq Computer Corporation

    Inventor： Abernathy, Michael G. ,  Fletcher, Angie M. ,  Santeler, Paul ,  Thoma III, Roy E.

    IPC: H05K1/00 ,  G06F1/16

    CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10689 ,  Y10T307/492

    Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace (202,216,248,274) is routed from the source terminal (200,214,236,260) of the net to a balanced junction (204,218,238,288) wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads (204,238). The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The 3 pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches. This pseudo-balanced load is connected to the source. In another alternative, two balanced subbranches have their balanced loads connected to a central balanced load. This balanced load may receive even further numbers of equal branches. The balanced load is connected to the source.

    Abstract translation: 一种电气系统，其中电路板上的导电迹线被路由以实现平衡网以减少由传输线反射引起的噪声。 轨迹（202,216,248,274）从网络的源终端（200,214,236,260）路由到平衡结（204,218,238,288），其中如果存在奇数个负载终端或负载，则平衡结位于一个负载（204,238 ）。 剩余的负载被分组成分支，其中每个分支包括相等数目的负载。 轨迹在每个分支的每个负载之间路由，以将每个分支的负载串联连接在一起，或者，轨迹从分支负载的中心一个路由到每个剩余的分支负载，形成子分支。 在替代实施例中，开发了平衡分支。 平衡负载连接到伪平衡负载，其进一步接收相等数量的分支。 然后，3个伪平衡负载连接到另一个可以接收相等数量的分支的伪平衡负载。 该伪平衡负载连接到源。 在另一个替代方案中，两个平衡子分支具有连接到中心平衡负载的平衡负载。 这种平衡负载可以接收更多数量的相等分支。 平衡负载连接到源。

Patent Agency Ranking