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    LEVEL SHIFTER
    1.
    发明授权
    LEVEL SHIFTER 有权

    公开(公告)号：EP3272013B1

    公开(公告)日：2019-11-13

    申请号：EP16704531.9

    申请日：2016-01-29

    申请人： Peregrine Semiconductor Corporation

    发明人： GREEN, Merlin ,  BURGENER, Mark L. ,  SWONGER, James W. ,  ABESINGHA, Buddhika ,  REEDY, Ronald Eugene

    IPC分类号： H03K17/689 ,  H03K19/0185

    摘要： Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

    Tuning capacitance to enhance FET stack voltage withstand
    2.
    发明授权
    Tuning capacitance to enhance FET stack voltage withstand 有权
    调谐电容以增强FET叠层耐压

    公开(公告)号：EP2148442B1

    公开(公告)日：2017-06-07

    申请号：EP09174085.2

    申请日：2007-04-27

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： Englekirk, Robert Mark

    IPC分类号： H03K17/693 ,  H01P1/15 ,  H04B1/48 ,  H03K17/10 ,  H03K17/16 ,  H03K17/687 ,  H03K17/06

    CPC分类号： H03K17/6871 ,  H01H11/00 ,  H03K17/102 ,  H03K17/161 ,  H03K17/693 ,  H03K2017/066 ,  Y10T29/49105

    摘要： An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

    摘要翻译： 用于可控制地承受施加的RF电压Vsw的RF开关或者制造这种开关的方法，其包括串联连接的组成FET的串，其中每对相邻FET之间具有串的节点。 该方法包括控制串的不同节点之间的电容以有效地调谐串，这将减少分布在每个组成FET上的RF开关电压的变化，由此增强开关击穿电压。 例如，通过在串的节点之间布置电容特征和/或通过改变不同组成FET的设计参数来控制电容。 对于每个节点，每个重要电容器的乘积之和乘以出现在其上的Vsw的比例可以被控制为大约为零。

    Tuning and control of an acoustic wave filter via a capacitor bank
    5.
    发明公开
    Tuning and control of an acoustic wave filter via a capacitor bank 有权
    通过电容器组对声波滤波器进行调谐和控制

    公开(公告)号：EP2843834A3

    公开(公告)日：2015-04-29

    申请号：EP14003070.1

    申请日：2011-12-09

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： Burgener, Mark L. ,  Cable, James S.

    IPC分类号： H03H9/54 ,  H03H9/64 ,  H03H9/70 ,  H03H9/72

    CPC分类号： H03H9/54 ,  H03H7/40 ,  H03H7/48 ,  H03H9/542 ,  H03H9/547 ,  H03H9/64 ,  H03H9/6403 ,  H03H9/6409 ,  H03H9/6483 ,  H03H9/6489 ,  H03H9/706 ,  H03H9/725 ,  H03H2009/02204 ,  H03H2210/015 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/04 ,  H03H2240/00 ,  H03H2250/00 ,  H03J2200/10

    摘要： In an acoustic wave filter a differential between the target/designed load on the input node or the target/designed load on the output node of a filter module (450) may affect its performance. The tunable filter is configured to reduce effects of impedance mismatches between the input and output loads (VSWR other than expected by filter module nominally). A variable capacitor (98A, 98B, 98C) is employed to modulate acoustic wave resonators (80A, 80B, 80C) to reduce a input signal insertion loss due to an unexpected or non-conforming VSWR (not equal to VSWR the filter model was designed to process). A PROM (448) is configured to include variable capacitor deltas for various VSWR. The control logic module may sense the output load, determine the VSWR differential, and choose the closest set of variable capacitor deltas from the PROM.

    摘要翻译： 在声波滤波器中，输入节点上的目标/设计负载或滤波器模块（450）的输出节点上的目标/设计负载之间的差可能影响其性能。 可调滤波器配置为减少输入和输出负载之间阻抗失配的影响（VSWR与标称滤波器模块预期的不同）。 采用可变电容器（98A，98B，98C）来调制声波谐振器（80A，80B，80C）以减小由于意想不到的或不一致的VSWR引起的输入信号插入损耗（不等于设计滤波器模型的VSWR 处理）。 PROM（448）被配置为包括用于各种VSWR的可变电容器增量。 控制逻辑模块可以感测输出负载，确定VSWR差分，并从PROM中选择最接近的一组可变电容器增量。

    Tuning and control of an acoustic wave filter via a capacitor bank
    6.
    发明公开
    Tuning and control of an acoustic wave filter via a capacitor bank 有权
    调整和利用声波与电容器组的帮助下工作的过滤器的控制

    公开(公告)号：EP2843834A1

    公开(公告)日：2015-03-04

    申请号：EP14003070.1

    申请日：2011-12-09

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： Burgener, Mark L. ,  Cable, James S.

    IPC分类号： H03H9/54 ,  H03H9/64 ,  H03H9/70 ,  H03H9/72

    CPC分类号： H03H9/54 ,  H03H7/40 ,  H03H7/48 ,  H03H9/542 ,  H03H9/547 ,  H03H9/64 ,  H03H9/6403 ,  H03H9/6409 ,  H03H9/6483 ,  H03H9/6489 ,  H03H9/706 ,  H03H9/725 ,  H03H2009/02204 ,  H03H2210/015 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/04 ,  H03H2240/00 ,  H03H2250/00 ,  H03J2200/10

    摘要： In an acoustic wave filter a differential between the target/designed load on the input node or the target/designed load on the output node of a filter module (450) may affect its performance. The tunable filter is configured to reduce effects of impedance mismatches between the input and output loads (VSWR other than expected by filter module nominally). A variable capacitor (98A, 98B, 98C) is employed to modulate acoustic wave resonators (80A, 80B, 80C) to reduce a input signal insertion loss due to an unexpected or non-conforming VSWR (not equal to VSWR the filter model was designed to process). A PROM (448) is configured to include variable capacitor deltas for various VSWR. The control logic module may sense the output load, determine the VSWR differential, and choose the closest set of variable capacitor deltas from the PROM.

    摘要翻译： 在弹性波滤波器的输入节点或过滤器模块（450）的输出节点上的目标/设计载荷上的目标/设计负载之间的差可能会影响其性能。 可调谐滤波器被配置以降低输入和输出负载之间的阻抗失配的影响（VSWR不同于通过过滤器模块名义上预期）。 可变电容器（98A，98B，98C）被用于调制声波谐振器（80A，80B，80C），以减少一个输入的信号插入损耗由于意外或不符合要求的VSWR（不等于VSWR其中设计了滤波器模型 处理）。 甲PROM（448）被配置为包括用于各种VSWR可变电容器的增量。 控制逻辑模块可以感测该输出负载的，确定性的矿井的VSWR差，并选择最接近的组从PROM可变电容器三角洲。

    INTEGRATED RF FRONT END
    7.
    发明授权
    INTEGRATED RF FRONT END 有权
    集成RF前端

    公开(公告)号：EP1774620B1

    公开(公告)日：2014-10-01

    申请号：EP05763216.8

    申请日：2005-06-23

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： BURGENER, Mark, L. ,  CABLE, James, S.

    IPC分类号： H01Q11/12 ,  H04B1/04 ,  H04B1/48 ,  H03G3/30 ,  H03F3/217

    CPC分类号： H04B1/48 ,  H01L27/0248 ,  H01Q23/00 ,  H03F1/0205 ,  H03F1/56 ,  H03F1/565 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/387 ,  H03F2200/451 ,  H03G3/3042 ,  H03G11/00 ,  H04B1/0053 ,  H04B1/0475 ,  H04L27/04

    摘要： A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

    Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device
    8.
    发明授权
    Method and Apparatus for use in Digitally Tuning a Capacitor in an Integrated Circuit Device 有权
    在集成电路器件的方法和用于在电容器的所述数字调谐装置使用

    公开(公告)号：EP2568608B1

    公开(公告)日：2014-05-14

    申请号：EP12194187.6

    申请日：2009-03-02

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： Ranta, Tero Tapio

    IPC分类号： H03M1/80 ,  H03M1/10

    CPC分类号： H03H11/28 ,  H01F21/12 ,  H01G4/002 ,  H01G7/00 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/60 ,  H03H7/0153 ,  H03H7/38 ,  H03J3/20 ,  H03J2200/10 ,  H03K17/102 ,  H03K17/162 ,  H03K17/687 ,  H03M1/1061 ,  H03M1/804

    摘要： A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.

    Low-noise high efficiency bias generation circuits and method
    10.
    发明公开
    Low-noise high efficiency bias generation circuits and method 审中-公开
    Lärmarme，hocheffiziente Vorspannungserzeugungsschaltung und Verfahren

    公开(公告)号：EP2385616A2

    公开(公告)日：2011-11-09

    申请号：EP11154279.1

    申请日：2009-07-17

    申请人： PEREGRINE SEMICONDUCTOR CORPORATION

    发明人： Kim, Tae Youn ,  Englekirk, Robert Mark ,  Kelly, Dylan J.

    IPC分类号： H02M3/07 ,  H03F1/26

    CPC分类号： H03F1/26 ,  H02M3/07 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2203/45138 ,  H03F2203/45188 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45471 ,  H03F2203/45642 ,  H03H11/245 ,  H03K17/145

    摘要： A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

    摘要翻译： 由有助于低噪声和/或高效率偏置的许多特征的任何一个或任何实际组合限定的偏置产生方法或装置，包括：具有电荷泵控制时钟输出，其波形具有有限的谐波含量或失真，与 正弦波 具有环形振荡器以产生电荷泵时钟，该时钟包括由共源共栅器件限制的反相器电流，并实现基本的轨到轨输出幅度; 具有可选择的启动和/或相位锁定特征的差分环形振荡器，以产生适当匹配且具有适当相位的两相输出; 具有产生电荷泵时钟的小于五级的环形振荡器; 将时钟输出电容耦合到一些或全部电荷转移电容器开关; 通过仅在出现在端子之间的波形的部分期间在输出端之间传导的“有源偏置电阻器”电路将与电容耦合到驱动信号的FET偏压到偏置电压，和/或其中产生偏置电压 通过在所述波形的周期切换小电容。 阈值电压偏置电压产生电路可以用于偏置产生的电荷泵可以包括也适用于其他用途的OTA的调节反馈回路，OTA具有控制差分放大器中的电流镜像比的比率控制输入 并且可选地具有包括由第二差分放大器产生的反相输出的差分输出，其可选地包括由相同比例控制输入控制的可变比率电流镜。 因此，比率控制输入可以控制OTA的差分输出的共模电压。 围绕OTA的控制回路可以被配置为控制一个或多个可变比电流镜的比率，其可以特别地控制输出共模电压，并且可以控制它，使得反相输出电平跟踪非反相输出电平 使放大器充当高增益积分器。