公开(公告)号：EP1654753A4

公开(公告)日：2009-01-21

申请号：EP04780916

申请日：2004-08-11

申请人： ADVANCED INTERCONNECT TECH LTD

发明人： ISLAM SHAFIDUL ,  LAU DANIEL KWOK ,  SAN ANTONIO ROMARICO SANTOS ,  SUBAGIO ANANG ,  MCKERREGHAN MICHAEL HANNAN ,  LITILIT EDMUNDA GUT-OMEN

IPC分类号： H01L23/495 ,  H01L20060101 ,  H01L23/31

CPC分类号： H01L23/3114 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

摘要： A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and another end (68) disposed proximate the die (14). Extending from opposite ends of the interposer (64) are a board connecting post (70) and a support post (74). A bond site (78) is formed on a surface of the interposer (64) opposite the support post (74). Each of the leads (60) is electrically connected to an associated input/output (I/O) pad (80) on the die (14) via wirebonding, tape bonding, or flip-chip attachment to the bond site (78). Where wirebonding is used, a wire electrically connecting the I/O pad (80) to the bond site (78) may be wedge bonded to both the I/O pad (80) and the bond site (78). The support post (74) provides support to the end (68) of the interposer (64) during the bonding and coating processes.(FIG. 3).

公开(公告)号：EP1668686A4

公开(公告)日：2006-09-13

申请号：EP04781479

申请日：2004-08-18

申请人： ADVANCED INTERCONNECT TECH LTD

发明人： ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

IPC分类号： H01L21/44 ,  H01L20060101 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10

CPC分类号： H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/84439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.

摘要翻译： 半导体器件封装包括导电引线框架，其具有设置在封装的周边的多个柱。 每个柱具有设置在第一封装面处的第一接触表面和设置在第二封装面处的第二接触表面。 引线框架还包括设置在第二封装面处的多个柱延伸部。 每个柱延伸部包括形成在与第二封装面相对的柱延伸部的表面上的粘结部位。 半导体器件上的至少一个I / O焊盘使用引线接合，带自动接合或倒装芯片方法在接合位置处电连接到柱延伸部。 可以使用具有预成形引线的引线框架来组装封装，带有或不带有胶带，或使用部分蚀刻的引线框架。 可以形成半导体器件封装的堆叠。