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    SEMICONDUCTOR ELEMENT, ELECTRIC APPARATUS, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTING STRUCTURAL BODY
    5.
    发明公开
    SEMICONDUCTOR ELEMENT, ELECTRIC APPARATUS, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTING STRUCTURAL BODY 审中-公开
    HALBLEITERELEMENT，ELEKTRISCHE VORRICHTUNG，BIDIREKTIONALER FELDEFFEKTTRANSISTOR UND MONTAGEBAUTEIL

    公开(公告)号：EP2988324A4

    公开(公告)日：2017-06-14

    申请号：EP14889300

    申请日：2014-11-18

    Applicant: POWDEC KK

    Inventor： ECHIGOYA SHOKO ,  NAKAMURA FUMIHIKO ,  YAGI SHUICHI ,  MATSUMOTO SOUTA ,  KAWAI HIROJI

    IPC: H01L29/778 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/861 ,  H01L29/872

    CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7393 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/81 ,  H01L2224/85

    Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped Al x Ga 1-x N layer 12 with a thickness not smaller than 25nm and not larger than 47nm and 0.17‰¤x‰¤0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10 -18 ) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w[cm -3 ] of the p-type GaN layer 14, tR‰¥0.864/(x-0.134)+46.0 [nm] is satisfied. The p-electrode contact region comprises a p-type GaN contact layer formed to be in contact with the p-type GaN layer 14 and a p-electrode that is in contact with the p-type GaN contact layer.

    Abstract translation: 本发明提供一种半导体器件和双向场效应晶体管，其能够容易地克服使用偏振超结的半导体器件中高压电阻与高速度之间的折衷关系，实现高电压电阻和消除电流崩溃的发生 ，高速运转，损失更低。 该半导体器件包括极化超结区和p电极接触区。 偏振超结区包括未掺杂的GaN层11，厚度不小于25nm且不大于47nm和0.17‰x‰0.35的未掺杂的Al x Ga 1-x N层12，未掺杂的GaN层13和 p型GaN层14.当对于未掺杂的GaN层13的厚度u [nm]，将减小的厚度t R定义为t R = u + v（1 + w×10 -18）时，厚度v [nm] 并且p型GaN层14的Mg浓度w [cm -3]满足tR≥0.864/（x-0.134）+46.0 [nm]。 p电极接触区域包括形成为与p型GaN层14接触的p型GaN接触层和与p型GaN接触层接触的p电极。

    SINGULATION OF IC PACKAGES
    6.
    发明公开
    SINGULATION OF IC PACKAGES 有权
    VEREINZELUNG VON IC-GE​​HÄUSEN

    公开(公告)号：EP2622635A4

    公开(公告)日：2017-03-01

    申请号：EP10857636

    申请日：2010-09-29

    Applicant: NXP BV

    Inventor： LI MARTIN KA SHING ,  LEUNG MAX ,  UMALI POMPEO

    IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495

    CPC classification number: H01L21/78 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85

    Abstract: A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts (32) extending fully through the leadframe (16) and encapsulation layer (14), and defining rows of the array. The cuts terminate before the beginning and end of the rows such that the integrity of the array is maintained by edge portions (34) at the ends of the rows. After plating contact pads (18), a second series of parallel cuts (36) is made extending fully through the leadframe (16) and encapsulation layer (14). This separates the array into columns thereby providing singulation of packages between the edge portions (34).

    Abstract translation: 将封装的集成电路的二维阵列划分成单独的集成电路封装的方法使用完全延伸穿过引线框架（16）和封装层（14）并且定义阵列的行的第一系列并行切割（32）。 切割在行的开始和结束之前终止，使得阵列的完整性由行的端部处的边缘部分（34）维持。 在电镀接触焊盘（18）之后，使第二系列平行切口（36）完全延伸穿过引线框架（16）和封装层（14）。 这将阵列分成列，从而在边缘部分（34）之间提供封装的单一化。

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