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公开(公告)号：EP3563432A1
公开(公告)日：2019-11-06
申请号：EP16925528.8
申请日：2016-12-28
申请人： INTEL Corporation
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公开(公告)号：EP1573803A2
公开(公告)日：2005-09-14
申请号：EP03814832.6
申请日：2003-12-15
申请人： INTEL CORPORATION
发明人： DOCZY, Mark , KEATING, Steven , KAVALIEROS, Jack , DOYLE, Brian , BARNS, Chris , BARNAK, John , MCSWINEY, Michael , BRASK, Justin
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
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3.发明授权A SEMICONDUCTOR DEVICE WITH A HIGH-K GATE DIELECTRIC AND A METAL GATE ELECTRODE 有权与栅介质高K-GATE和金属引脚半导体COMPONENT
公开(公告)号：EP1790006B1
公开(公告)日：2011-08-24
申请号：EP05770566.7
申请日：2005-07-08
申请人： Intel Corporation
发明人： DOCZY, Mark , KAVALIEROS, Jack , METZ, Matthew , BRASK, Justin , DATTA, Suman , CHAU, Robert
IPC分类号： H01L21/8238 , H01L21/28
CPC分类号： H01L21/28194 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.
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4.发明公开
公开(公告)号：EP1620898A1
公开(公告)日：2006-02-01
申请号：EP03808513.0
申请日：2003-12-18
申请人： INTEL CORPORATION
发明人： CHAU, Robert , DOCZY, Mark , KUHN, Markus
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L29/517 , H01L29/518
摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also described is a semiconductor device that comprises a metal gate electrode that is formed on a dielectric layer, which is formed on a substrate. The metal gate electrode includes a sufficient amount of an impurity to shift the workfunction of the metal gate electrode by at least about 0.1 eV.
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5.发明公开PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY 审中-公开PROCESS TO TO体衬底和制品由其得到的平面和非平面CMOS晶体管的INTEGRATE
公开(公告)号：EP1929516A2
公开(公告)日：2008-06-11
申请号：EP06815547.2
申请日：2006-09-26
申请人： Intel Corporation
发明人： KAVALIEROS, Jack , BRASK, Justin , DOYLE, Brian , SHAH, Uday , DATTA, Suman , DOCZY, Mark , METZ, Matthew , CHAU, Robert
IPC分类号： H01L21/8234 , H01L21/336 , H01L29/10
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar (10) and non-planar (20, 30) transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
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公开(公告)号：EP1794790A1
公开(公告)日：2007-06-13
申请号：EP05817332.9
申请日：2005-09-16
申请人： Intel Corporation
发明人： DOCZY, Mark , BRASK, Justin , KAVALIEROS, Jack , BARNS, Chris , METZ, Matthew , DATTA, Suman , CHAU, Robert
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823437 , H01L21/823828
摘要： A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.
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公开(公告)号：EP1665349A2
公开(公告)日：2006-06-07
申请号：EP04784782.7
申请日：2004-09-23
申请人： INTEL CORPORATION
发明人： JIN, Been-Yih , DOYLE, Brian , HARELAND, Scott , DOCZY, Mark , METZ, Matthew , BOYANOV, Boyan , DATTA, Suman , KAVALIEROS, Jack , CHAU, Robert
IPC分类号： H01L21/20
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
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8.发明公开A METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC 审中-公开用于制造半导体器件的栅极电介质高K A方法
公开(公告)号：EP1604405A1
公开(公告)日：2005-12-14
申请号：EP03800030.3
申请日：2003-12-18
申请人： INTEL CORPORATION
发明人： BRASK, Justin , DOCZY, Mark , BARNAK, John , CHAU, Robert
IPC分类号： H01L29/51 , H01L21/28 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823814 , H01L21/823871 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer (110) on a substrate (100), then forming a capping (115) layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide (125) on the high-k gate dielectric layer, a gate electrode (120) is formed on the capping dielectric oxide.
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公开(公告)号：EP1573803B1
公开(公告)日：2013-06-05
申请号：EP03814832.6
申请日：2003-12-15
申请人： Intel Corporation
发明人： DOCZY, Mark , KEATING, Steven , KAVALIEROS, Jack , DOYLE, Brian , BARNS, Chris , BARNAK, John , MCSWINEY, Michael , BRASK, Justin
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
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10.发明授权USING DIFFERENT GATE DIELECTRICS WITH NMOS AND PMOS TRANSISTORS OF A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT 有权使用具有NMOS和PMOS晶体管INTEGRATEDKOMPLEMETÄREN互补金属氧化物半导体不同的栅极电介质
公开(公告)号：EP1761952B1
公开(公告)日：2012-10-24
申请号：EP05767666.0
申请日：2005-06-24
申请人： Intel Corporation
发明人： METZ, Matthew , DATTA, Suman , KAVALIEROS, Jack , DOCZY, Mark , BRASK, Justin , CHAU, Robert
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823857
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