摘要:
Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
摘要:
Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.
摘要:
Embodiments of the present invention provide a complementary tunneling field effect transistor and a manufacturing method therefor, which relate to the field of semiconductor technologies. The complementary tunneling field effect transistor can increase carrier tunneling efficiency and improve performance of the complementary tunneling field effect transistor. The transistor includes: a first drain region (20a) and a first source region (20b) that are disposed on a substrate (10), where the first drain region and the first source region include a first dopant; a first channel (30a) that is disposed on the first drain region and a second channel (30b) that is disposed on the first source region; a second source region (40a) that is disposed on the first channel and a second drain region (40b) that is disposed on the second channel, where the second source region and the second drain region include a second dopant; a first epitaxial layer (50a) that is disposed on the first drain region and the second source region, and a second epitaxial layer (50b) that is disposed on the second drain region and the first source region; and a first gate stack layer (60a) that is disposed on the first epitaxial layer, and a second gate stack layer (60b) that is disposed on the second epitaxial layer.
摘要:
A gate-all-around semiconductor device and a method for manufacturing a gate-all-around semiconductor device are disclosed. The gate-all-around (GAA) semiconductor device comprises a semiconductor substrate (100) comprising a first crystalline semiconductor material; two suspended nanowires (105a, 105b) horizontally adjacent at a distance D being located at least partially above and in between a pair of adjacent STI regions (101) and the two suspended nanowires being held in place by a source region (121) and a drain region (122) at both ends of the at least one suspended nanostructure, the two suspended nanowires comprising a third crystalline semiconductor material which is different from the first crystalline semiconductor material, wherein a cavity (114) is present between the suspended nanowires (105a, 105b), opposite sidewalls of the STI regions (101) and the semiconductor substrate (100), wherein the suspended nanowires are wrapped by a final gate stack and wherein the top surface and the sidewalls of the STI regions and the exposed surface of the semiconductor substrate from the cavity are also covered by the final gate stack and wherein distance D is larger than the thickness of the final gate stack and is smaller than the width of the cavity.
摘要:
Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
摘要:
A transistor includes a substrate, a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the layer is on the substrate and the layer extends substantially vertical to the substrate, a source electrode and a drain electrode connected to opposite ends of the two-dimensional material, a gate insulation layer on the two-dimensional material between the source electrode and the drain electrode, and a gate electrode on the gate insulation layer. Each layer includes a semiconductor having a two-dimensional crystal structure.
摘要:
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.
摘要:
Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600°C, and a polycrystalline or amorphous In x Ga y Al z N layer was obtained. When composition expressed with a general expression In x Ga y Al z N (where x+y+z=1.0) falls within a range of 0.3≤x≤1.0 and 0≤z≤0.4, a transistor 1 a exhibiting an ON/OFF ratio of 10 2 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAIN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.
摘要翻译:使用氮化物半导体层作为通道的晶体管被实验制造。 氮化物半导体层全部通过溅射法形成。 沉积温度设定在600℃以下,得到多晶或非晶In x Ga y Al z N层。 当用一般表达式In x Ga y Al z N(其中x + y + z = 1.0)表示的组成落在0.3‰×‰×1.0和0‰¤z‰¤0.4的范围内时,晶体管1a 可以获得10 2以上的ON / OFF比。 也就是说,即使是多晶或非晶体膜,也具有与单晶相同的电特性。 因此,可以提供一种半导体器件,其中严格地消除了对制造条件的限制,并且包括廉价且具有优异的电特性作为通道的InGaIN基氮化物半导体层。