TRANSITION METAL DICHALCOGENIDE SEMICONDUCTOR ASSEMBLIES
    4.
    发明公开
    TRANSITION METAL DICHALCOGENIDE SEMICONDUCTOR ASSEMBLIES 审中-公开
    ÜBERGANGSMETALLDICHALKOGENID-HALBLEITERANORDNUNGEN

    公开(公告)号:EP3120384A4

    公开(公告)日:2017-09-27

    申请号:EP14886408

    申请日:2014-03-21

    申请人: INTEL CORP

    摘要: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the transistor channel may be disposed between the second barrier and the first barrier, and a bandgap of the transistor channel may be less than a bandgap of the first barrier and less than a bandgap of the second barrier. Other embodiments may be disclosed and/or claimed.

    摘要翻译: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中,半导体组件可以包括柔性衬底,由第一过渡金属二硫属元素化物(TMD)材料形成的第一阻挡层,由第二TMD材料形成的晶体管沟道以及由第三TMD材料形成的第二阻挡层。 第一屏障可以设置在晶体管沟道和柔性衬底之间,晶体管沟道可以设置在第二屏障和第一屏障之间,并且晶体管沟道的带隙可以小于第一屏障的带隙并且小于 第二屏障的带隙。 其他实施例可以被公开和/或要求保护。

    COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR
    5.
    发明公开
    COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR 审中-公开
    互补隧穿场效应晶体管及其制造方法

    公开(公告)号:EP3193374A1

    公开(公告)日:2017-07-19

    申请号:EP15857108.3

    申请日:2015-04-27

    摘要: Embodiments of the present invention provide a complementary tunneling field effect transistor and a manufacturing method therefor, which relate to the field of semiconductor technologies. The complementary tunneling field effect transistor can increase carrier tunneling efficiency and improve performance of the complementary tunneling field effect transistor. The transistor includes: a first drain region (20a) and a first source region (20b) that are disposed on a substrate (10), where the first drain region and the first source region include a first dopant; a first channel (30a) that is disposed on the first drain region and a second channel (30b) that is disposed on the first source region; a second source region (40a) that is disposed on the first channel and a second drain region (40b) that is disposed on the second channel, where the second source region and the second drain region include a second dopant; a first epitaxial layer (50a) that is disposed on the first drain region and the second source region, and a second epitaxial layer (50b) that is disposed on the second drain region and the first source region; and a first gate stack layer (60a) that is disposed on the first epitaxial layer, and a second gate stack layer (60b) that is disposed on the second epitaxial layer.

    摘要翻译: 本发明的实施例提供一种互补隧穿场效应晶体管及其制造方法,涉及半导体技术领域。 互补隧穿场效应晶体管可以提高载流子隧穿效率并提高互补隧道场效应晶体管的性能。 晶体管包括:设置在衬底(10)上的第一漏极区(20a)和第一源极区(20b),其中第一漏极区和第一源极区包括第一掺杂剂; 设置在第一漏极区上的第一沟道(30a)和设置在第一源极区上的第二沟道(30b); 设置在所述第一沟道上的第二源极区域(40a)和设置在所述第二沟道上的第二漏极区域(40b),其中所述第二源极区域和所述第二漏极区域包括第二掺杂剂; 设置在所述第一漏极区域和所述第二源极区域上的第一外延层(50a)以及设置在所述第二漏极区域和所述第一源极区域上的第二外延层(50b) 以及设置在第一外延层上的第一栅堆叠层(60a)以及设置在第二外延层上的第二栅堆叠层(60b)。

    METHOD FOR MANUFACTURING A III-V GATE ALL AROUND SEMICONDUCTOR DEVICE
    6.
    发明公开
    METHOD FOR MANUFACTURING A III-V GATE ALL AROUND SEMICONDUCTOR DEVICE 有权
    在半导体器件周围制造III-V栅极的方法

    公开(公告)号:EP3185302A1

    公开(公告)日:2017-06-28

    申请号:EP17154908.2

    申请日:2015-03-25

    申请人: IMEC vzw

    摘要: A gate-all-around semiconductor device and a method for manufacturing a gate-all-around semiconductor device are disclosed. The gate-all-around (GAA) semiconductor device comprises a semiconductor substrate (100) comprising a first crystalline semiconductor material; two suspended nanowires (105a, 105b) horizontally adjacent at a distance D being located at least partially above and in between a pair of adjacent STI regions (101) and the two suspended nanowires being held in place by a source region (121) and a drain region (122) at both ends of the at least one suspended nanostructure, the two suspended nanowires comprising a third crystalline semiconductor material which is different from the first crystalline semiconductor material, wherein a cavity (114) is present between the suspended nanowires (105a, 105b), opposite sidewalls of the STI regions (101) and the semiconductor substrate (100), wherein the suspended nanowires are wrapped by a final gate stack and wherein the top surface and the sidewalls of the STI regions and the exposed surface of the semiconductor substrate from the cavity are also covered by the final gate stack and wherein distance D is larger than the thickness of the final gate stack and is smaller than the width of the cavity.

    摘要翻译: 公开了一种全环绕半导体器件和一种制造全环绕半导体器件的方法。 全环栅(GAA)半导体器件包括:半导体衬底(100),其包括第一晶体半导体材料; 以距离D水平相邻的两个悬浮纳米线(105a,105b)至少部分地位于一对相邻STI区域(101)之上和之间,并且两个悬置纳米线由源极区域(121)和 所述两个悬挂纳米线包括与所述第一晶体半导体材料不同的第三晶体半导体材料,其中空腔(114)存在于所述悬置纳米线(105a)之间,所述空腔(114)存在于所述悬置纳米线 ,所述STI区域(101)和所述半导体衬底(100)的相对侧壁,其中所述悬置纳米线由最终栅极叠层包裹,并且其中所述STI区域的顶表面和侧壁以及所述 来自所述空腔的半导体衬底也被所述最终栅极叠层覆盖,并且其中距离D大于所述最终栅极叠层的厚度且小于所述空腔的宽度 性。

    FIELD EFFECT TRANSISTOR CONSTRUCTIONS AND MEMORY ARRAYS
    9.
    发明公开
    FIELD EFFECT TRANSISTOR CONSTRUCTIONS AND MEMORY ARRAYS 有权
    场效应变压器设计和存储阵列

    公开(公告)号:EP3092660A4

    公开(公告)日:2016-12-21

    申请号:EP14878177

    申请日:2014-12-03

    摘要: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

    摘要翻译: 在一些实施例中,晶体管包括具有底部源极/漏极区域,第一绝缘材料,导电栅极,第二绝缘材料和顶部源极/漏极区域的堆叠。 堆叠具有垂直侧壁,其沿着底部源极/漏极区域具有底部部分,沿着导电栅极的中间部分以及沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料具有在大于约至小于或等于约的范围内的厚度; 和/或具有1个单层至7个单层的厚度。

    INGAALN-BASED SEMICONDUCTOR ELEMENT
    10.
    发明公开
    INGAALN-BASED SEMICONDUCTOR ELEMENT 审中-公开
    国际基准研究所

    公开(公告)号:EP3043389A1

    公开(公告)日:2016-07-13

    申请号:EP14840925.3

    申请日:2014-08-28

    IPC分类号: H01L29/786 H01L29/80

    摘要: Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600°C, and a polycrystalline or amorphous In x Ga y Al z N layer was obtained. When composition expressed with a general expression In x Ga y Al z N (where x+y+z=1.0) falls within a range of 0.3≤x≤1.0 and 0≤z≤0.4, a transistor 1 a exhibiting an ON/OFF ratio of 10 2 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAIN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.

    摘要翻译: 使用氮化物半导体层作为通道的晶体管被​​实验制造。 氮化物半导体层全部通过溅射法形成。 沉积温度设定在600℃以下,得到多晶或非晶In x Ga y Al z N层。 当用一般表达式In x Ga y Al z N(其中x + y + z = 1.0)表示的组成落在0.3‰×‰×1.0和0‰¤z‰¤0.4的范围内时,晶体管1a 可以获得10 2以上的ON / OFF比。 也就是说,即使是多晶或非晶体膜,也具有与单晶相同的电特性。 因此,可以提供一种半导体器件,其中严格地消除了对制造条件的限制,并且包括廉价且具有优异的电特性作为通道的InGaIN基氮化物半导体层。