公开(公告)号：EP3050062A1

公开(公告)日：2016-08-03

申请号：EP14847332.5

申请日：2014-08-26

申请人： Intel Corporation

发明人： PANGAL, Kiran ,  RAMANUJAN, Raj K. ,  FABER, Robert W. ,  SUNDARAM, Rajesh

IPC分类号： G11C13/00 ,  G11C11/21

CPC分类号： G11C13/0033 ,  G11C13/0004 ,  G11C2013/0076

摘要： Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.

公开(公告)号：EP3436920A1

公开(公告)日：2019-02-06

申请号：EP16897340.2

申请日：2016-03-31

申请人： INTEL Corporation

发明人： GUIM BERNAT, Francesc ,  WILLHALM, Thomas ,  KUMAR, Karthik ,  DIMITROV, Martin P. ,  RAMANUJAN, Raj K.

IPC分类号： G06F3/06

公开(公告)号：EP2656225A2

公开(公告)日：2013-10-30

申请号：EP11851888.5

申请日：2011-11-18

申请人： Intel Corporation

发明人： DAHLEN, Eric J. ,  HINTON, Glenn J. ,  RAMANUJAN, Raj K.

IPC分类号： G06F12/00

CPC分类号： G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

公开(公告)号：EP3382556A1

公开(公告)日：2018-10-03

申请号：EP18165216.5

申请日：2011-09-30

申请人： INTEL Corporation

发明人： Nale, Bill ,  RAMANUJAN, Raj K. ,  SWAMINATHAN, Muthukumar P. ,  THOMAS, Tessil ,  POLEPEDDI, Taarinya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F11/10 ,  G06F13/14 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42 ,  G06F13/36 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/40

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：EP3465444A1

公开(公告)日：2019-04-10

申请号：EP17722955.6

申请日：2017-04-27

申请人： Intel Corporation

发明人： GUIM BERNAT, Francesc ,  DURAN GONZALEZ, Alejandro ,  KUMAR, Karthik ,  WILLHALM, Thomas ,  RAMANUJAN, Raj K.

IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F9/50

公开(公告)号：EP3364304A1

公开(公告)日：2018-08-22

申请号：EP18165222.3

申请日：2011-09-30

申请人： INTEL Corporation

发明人： NALE, Bill ,  RAMANUJAN, Raj K. ,  SWAMINATHAN, Muthukumar P. ,  THOMAS, Tessil ,  POLEPEDDI, Taarinya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F11/10 ,  G06F13/14 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0811

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：EP3161622A1

公开(公告)日：2017-05-03

申请号：EP15810867.0

申请日：2015-06-01

申请人： Intel Corporation

发明人： RAMANUJAN, Raj K. ,  SANKARAN, Rajesh M. ,  NACHIMUTHU, Murugasamy K. ,  MANGOLD, Richard P.

IPC分类号： G06F9/44 ,  G06F12/02

CPC分类号： G06F3/0611 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/71 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4416 ,  G06F11/1417 ,  G06F11/3476 ,  G11C7/20

摘要： Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

摘要翻译： 的方法和装置，以加速引导时间的基于非易失性存储器（NVM）技术存储器调零进行说明。 ，实施例中的存储装置存储引导版本号对应于非易失性存储器的一部分。 存储器控制器逻辑使得响应于每个船随后发生的事件所存储的引导版本号的更新。 存储器控制器逻辑响应于读取手术针对非易失性存储器的所述部分与所存储的引导版本号和当前引导的版本号之间不匹配返回零。 其它实施例因此是游离缺失盘和要求保护的。

公开(公告)号：EP3014623A1

公开(公告)日：2016-05-04

申请号：EP14818140.7

申请日：2014-06-23

申请人： Intel Corporation

发明人： RAMANUJAN, Raj K.

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C14/0009 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0868 ,  G06F2212/311 ,  G06F2212/7203 ,  Y02D10/13

摘要： Memory devices, controllers, and electronic devices comprising memory devices are described. In one embodiment, a memory device comprises a volatile memory, a nonvolatile memory, and a controller comprising a memory buffer, and logic to transfer data between the nonvolatile memory and the volatile memory via the memory buffer in response to requests from an application, wherein data in the memory buffer is accessible to the application. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了包括存储器设备的存储器设备，控制器和电子设备。 在一个实施例中，存储器设备包括易失性存储器，非易失性存储器以及包括存储器缓冲器的控制器，以及用于响应于来自应用的请求而经由存储器缓冲器在非易失性存储器与易失性存储器之间传输数据的逻辑，其中 内存缓冲区中的数据可供应用程序访问。 其他实施例也被公开和要求保护。

公开(公告)号：EP3712774A1

公开(公告)日：2020-09-23

申请号：EP20173833.3

申请日：2011-09-30

申请人： INTEL Corporation

发明人： RAMANUJAN, Raj K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille C. ,  ZIMMERMAN, David J. ,  SWAMINATHAN, Muthukumar P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan J. ,  COURY, Bassam N. ,  HINTON, Glenn J.

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/08

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."

公开(公告)号：EP3014623B1

公开(公告)日：2019-03-13

申请号：EP14818140.7

申请日：2014-06-23

申请人： Intel Corporation

发明人： RAMANUJAN, Raj K.

IPC分类号： G11C7/10 ,  G11C7/22 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/02 ,  G06F12/0868 ,  G06F3/06