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11 条记录 (耗时 0.011 秒)

    PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY
    1.
    发明公开
    PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY 审中-公开
    EINEN SPEICHER的BEREITSTELLUNG VONSTROMVERFÜGBARKEITSINFORMATIONEN

    公开(公告)号：EP3149733A1

    公开(公告)日：2017-04-05

    申请号：EP15800213.9

    申请日：2015-05-14

    申请人： Micron Technology, Inc.

    发明人： MIRICHIGNI, Graziano ,  VILLA, Corrado

    IPC分类号： G11C5/14 ,  G11C16/30

    CPC分类号： G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/14

    摘要： The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

    摘要翻译： 本公开包括用于向存储器提供功率可用性信息的装置和方法。 许多实施例包括存储器和控制器。 控制器被配置为向存储器提供功率和功率可用性信息，并且存储器被配置为至少部分地基于功率可用性信息来确定是否调整其操作。

    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES
    7.
    发明公开
    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开
    器件和方法的存储操作变延迟时间

    公开(公告)号：EP2912558A1

    公开(公告)日：2015-09-02

    申请号：EP13849956.1

    申请日：2013-10-25

    申请人： Mirichigni, Graziano ,  Villa, Corrado ,  Porzio, Luca ,  Micron Technology, Inc.

    发明人： MIRICHIGNI, Graziano ,  VILLA, Corrado ,  PORZIO, Luca

    IPC分类号： G06F13/14 ,  G06F13/38 ,  G06F12/00

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1063

    摘要： Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

    PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY
    9.
    发明公开
    PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY 审中-公开

    公开(公告)号：EP3537441A1

    公开(公告)日：2019-09-11

    申请号：EP19170778.5

    申请日：2015-05-14

    申请人： Micron Technology, Inc.

    发明人： MIRICHIGNI, Graziano ,  VILLA, Corrado

    IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C11/4072 ,  G11C11/4074 ,  G06F13/16

    摘要： A method of operating a memory device (104) includes a receiving signalling from a host (102) at the memory device and identifying, based at least in part on the signalling from the host, an indication that power to the memory device is being turned off. An amount of time for which the memory device can continue to operate in a present operating condition, is determined, wherein the amount of time is any one of unlimited amount of time, a first amount of time that is less than the unlimited amount of time, a second amount of time that is less than the first amount of time, or a third amount of time that is less than the second amount of time. The memory device is operated in the present operating condition for the amount of time that has been determined. Memory apparatus (100) is provided which includes a memory (110), and a controller (108) operating the memory, in accordance with the method just described.

    APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS
    10.
    发明公开
    APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS 审中-公开
    VORRICHTUNGEN UND VERFAHREN ZURDURCHFÜHRUNGMEHRERER SPEICHEROPERATIONEN

    公开(公告)号：EP3140833A1

    公开(公告)日：2017-03-15

    申请号：EP15788901.5

    申请日：2015-05-04

    申请人： Micron Technology, Inc.

    发明人： BALLUCHI, Daniele ,  VILLA, Corrado

    IPC分类号： G11C13/00 ,  G11C11/00

    CPC分类号： G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

    摘要： The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

    摘要翻译： 所公开的技术涉及被配置为响应于通过存储器控制器接收的单个命令和执行多址访问操作的方法来执行多次访问操作的存储器件。 在一个方面，存储器件包括包括多个存储器单元和存储器控制器的存储器阵列。 存储器控制器被配置为接收指定对存储器阵列执行的多个存储器访问操作的单个命令。 存储器控制器还被配置为使得对存储器阵列执行指定的多个存储器访问操作。