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13 条记录 (耗时 0.013 秒)

    ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE
    2.
    发明公开
    ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE 有权
    稳健半导体元件宽高比HIGH

    公开(公告)号：EP2334589A1

    公开(公告)日：2011-06-22

    申请号：EP09787279.0

    申请日：2009-09-24

    申请人： NXP B.V.

    发明人： ROOZEBOOM, Freddy ,  GOOSSENS, Martijn ,  BESLING, Willem Frederik Adrianus ,  VERHAEGH, Nynke

    IPC分类号： B81B1/00 ,  B81C99/00 ,  H01L29/41 ,  H01L31/0224

    CPC分类号： H01L29/41 ,  B81B3/007 ,  B81B2201/06 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L28/91

    摘要： The invention relates to an semiconductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.

    DC-TO-DC CONVERTER COMPRISING A RECONFIGURABLE CAPACITOR UNIT
    3.
    发明公开
    DC-TO-DC CONVERTER COMPRISING A RECONFIGURABLE CAPACITOR UNIT 有权
    与重新配置的电容单元DC-DC转换器

    公开(公告)号：EP2147499A2

    公开(公告)日：2010-01-27

    申请号：EP08751175.4

    申请日：2008-05-08

    申请人： NXP B.V.

    发明人： KLOOTWIJK, Johan, H. ,  BERGVELD, Hendrik, J. ,  ROOZEBOOM, Freddy ,  REEFMAN, Derk ,  RUIGROK, Jaap

    IPC分类号： H02M3/07 ,  H01L27/08

    CPC分类号： H01L27/0805 ,  H02M3/07

    摘要： The present invention relates to a configurable trench multi-capacitor device comprising a trench in a semiconductor substrate. The trench has a lateral extension exceeding 10 micrometer and a trench filling includes a number of at least four electrically conductive capacitor-electrode layers. A switching unit is provided that comprises a plurality of switching elements electrically interconnected between different capacitor-electrode layers of the trench filling. A control unit is connected with the switching unit and configured to generate and provide to the switching unit respective control signals for forming a respective one of a plurality of multi-capacitor configurations using the capacitor-electrode layers of the trench filling.

    INTEGRATED CAPACITOR ARRANGEMENT FOR ULTRAHIGH CAPACITANCE VALUES
    4.
    发明公开
    INTEGRATED CAPACITOR ARRANGEMENT FOR ULTRAHIGH CAPACITANCE VALUES 审中-公开
    集成电容器装置，超高容量值

    公开(公告)号：EP1949418A2

    公开(公告)日：2008-07-30

    申请号：EP06821292.7

    申请日：2006-11-02

    申请人： NXP B.V.

    发明人： ROOZEBOOM, Freddy ,  KLOOTWIJK, Johan, H. ,  KEMMEREN, Antonius, L., A., M. ,  REEFMAN, Derk ,  VERHOEVEN, Johannes, F., C., M.

    IPC分类号： H01L21/02

    CPC分类号： H01L28/91 ,  H01L27/0805 ,  H01L27/1087 ,  H01L29/945

    摘要： The present invention relates to an electronic device (300) comprising at least one trench capacitor (302) that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence (308) of at least two dielectric layers (312, 316) and at least two electrically conductive layers (314, 318) is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads (332, 334, 340) is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. By providing an individual internal contact pad for each of the electrically conductive layers, a range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value. The electronic device of the invention thus provides a flexible trench-capacitor manufacturing platform for a multitude of combinations of electrically conductive layers with each other, or, when multiple trenches are used, between electrically conductive layers of different trench capacitors. On-chip applications such as a charge-pump circuit or a DC-to-DC voltage converter are claimed that benefit from the ultra-high capacitance density and the high breakdown voltage that can be achieved with the electronic device of the invention.

    PRODUCING A COVERED THROUGH SUBSTRATE VIA USING A TEMPORARY CAP LAYER
    7.
    发明公开
    PRODUCING A COVERED THROUGH SUBSTRATE VIA USING A TEMPORARY CAP LAYER 有权
    赫尔辛基爱丁堡基督教堂 - 德黑兰关系

    公开(公告)号：EP1949432A2

    公开(公告)日：2008-07-30

    申请号：EP06821309.9

    申请日：2006-11-03

    申请人： NXP B.V.

    发明人： KLOOTWIJK, Johan, H. ,  KEMMEREN, Antonius, L., A., M. ,  DEKKER, Ronald ,  VAN GRUNSVEN, Eric, C., E. ,  ROOZEBOOM, Freddy

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/764 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a method for producing a substrate with at least one covered via that electrically and preferably also thermally connects a first substrate side with an opposite second substrate side. The processing involves forming a trench on a the first substrate side remains and covering the trench with a permanent layer on top of a temporary, sacrificial cap-layer, which is decomposed in a thermal process step. The method of the invention provides alternative ways to remove decomposition products of the sacrificial cap-layer material without remaining traces or contamination even in the presence of the permanent layer. This is, according to a first aspect of the invention, achieved by providing the substrate trench with an overcoat layer that has holes. The holes in the overcoat layer leave room for the removal of the decomposition products of the cap-layer material. According to the second aspect of the invention, opening the covered trench from the second substrate side and allowing the cap-layer material to be removed through that opening provides a solution. Both methods of the present invention are based on the common idea of using a temporary cap-layer even in a situation where the substrate opening is permanently covered before the removal of the temporary cap-layer.

    摘要翻译： 本发明涉及一种用于制造具有至少一个覆盖通孔的基板的方法，所述至少一个覆盖通孔电连接并且优选也将第一基板侧与相对的第二基板侧热连接。 涉及在第一衬底侧上形成沟槽的处理保留并且在临时牺牲帽层的顶部上具有永久层覆盖沟槽，其在热处理步骤中被分解。 本发明的方法提供了即使在存在永久层的情况下除去牺牲帽层材料的分解产物而不留下痕迹或污染物的替代方法。 根据本发明的第一方面，这是通过为衬底沟槽提供具有孔的外涂层而实现的。 外涂层中的孔留下去除盖层材料的分解产物的空间。 根据本发明的第二方面，从第二基板侧打开被覆盖的沟槽并且允许通过该开口去除盖层材料提供了一种解决方案。 本发明的两种方法都基于即使在去除临时盖层之前基材开口被永久地覆盖的情况下也使用临时盖层的常见思想。

    PLANAR, MONOLITHICALLY INTEGRATED COIL
    8.
    发明公开
    PLANAR, MONOLITHICALLY INTEGRATED COIL 有权
    平面单片集成COIL

    公开(公告)号：EP2297751A2

    公开(公告)日：2011-03-23

    申请号：EP09772999.0

    申请日：2009-06-30

    申请人： NXP B.V.

    发明人： ROOZEBOOM, Freddy ,  REEFMAN, Derk ,  KLOOTWIJK, Johan Hendrik ,  TIEMEIJER, Lukas Frederik ,  RUIGROK, Jaap

    IPC分类号： H01F27/36

    CPC分类号： H01F17/0006 ,  H01F27/365 ,  H01F2017/0066 ,  H01F2017/008

    摘要： The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. Inmany applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 μH, and must have an equivalent series resistance of less than 0.1 Ω. For this reason, those inductors are always bulky components, of a typical size of 2 x 2 x 1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 veryhigh DC resistance values.