公开(公告)号：EP3151273A1

公开(公告)日：2017-04-05

申请号：EP16194094.5

申请日：2014-12-03

Applicant: NXP USA, Inc.

Inventor： SZYMANOWSKI, Margaret A. ,  MUSA, Sarmad K ,  SANTOS, Fernando A ,  SHAH, Mahesh K.

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A system and method for packaging a semiconductor device (20) that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate (74) on which a first circuit (22) and a second circuit (24) are formed proximate to each other. An isolation wall (50) of electrically conductive material is located between the first circuit and the second circuit, the isolation wall (50) being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. The isolation wall (50) includes a plurality of holes (52) through which encapsulation material may flow during a process of making the semiconductor device (10). Several types of isolation wall (50) are presented.

Abstract translation: 提出了一种用于封装包括壁以减少电磁耦合的半导体器件（20）的系统和方法。 半导体器件具有基板（74），第一电路（22）和第二电路（24）彼此靠近地形成在其上。 导电材料的隔离壁（50）位于第一电路和第二电路之间，隔离壁（50）构造成在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 隔离壁（50）包括多个孔（52），在制造半导体器件（10）的过程中，封装材料可以通过该孔（52）流动。 提出了几种类型的隔离墙（50）。