公开(公告)号：EP3780074A3

公开(公告)日：2021-06-02

申请号：EP20191180.7

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  DERAI, Michele ,  MAGNI, Pierangelo

IPC: H01L21/56 ,  H01L21/60 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/367 ,  H01L23/31

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).

公开(公告)号：EP3832701A1

公开(公告)日：2021-06-09

申请号：EP20210546.6

申请日：2020-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  MAGNI, Pierangelo

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538

Abstract: A method of manufacturing semiconductor devices (10) comprises:
- providing a plastic material substrate (100) having at least one die mounting location (102) for a semiconductor die (104),
- forming metallic traces (108a, 108b) on selected areas of the plastic material substrate (100), wherein the metallic traces (108a, 108b) provide electrically-conductive paths for coupling to the semiconductor die (104),
- attaching the semiconductor die (104) onto the at least one die mounting location (102),
- bonding the semiconductor die (104) attached onto the at least one die mounting location (102) to selected ones of the metallic traces (108a, 108b) formed on the plastic material substrate (100),
- molding package material (110) onto the semiconductor die (104) attached onto the at least one die mounting location (102).

公开(公告)号：EP3780074A2

公开(公告)日：2021-02-17

申请号：EP20191180.7

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： ZIGLIOLI, Federico Giovanni ,  PINTUS, Alberto ,  DERAI, Michele ,  MAGNI, Pierangelo

IPC: H01L21/56 ,  H01L21/60 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/36

Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).

公开(公告)号：EP1945561A2

公开(公告)日：2008-07-23

申请号：EP06777802.7

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02

CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract translation: 具有A衬底级组件的半导体材料的器件衬底具有顶面和外壳的第一集成器件，包括器件衬底内形成的掩埋空腔，并用悬浮在在顶面的接近掩埋空腔的膜。 甲封盖衬底耦合到所述顶面之上的器件衬底，以便覆盖所述第一集成器件在寻求做的膜上方提供第一空白空间的方式。 电接触元件电连接与所述衬底级组件的外部集成器件。 在一个实施例中，器件衬底至少集成设置有respectivement膜的进一步集成器件，和另外的空的空间，从所述第一空的空间流体地隔离，则在进一步的集成器件的respectivement膜提供。