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公开(公告)号：EP4148993B1
公开(公告)日：2024-11-06
申请号：EP22185925.9
申请日：2022-07-20
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公开(公告)号：EP3574675B1
公开(公告)日：2024-10-30
申请号：EP18751975.6
申请日：2018-02-11
发明人： JHENG, Yu-Syuan , NUGGEHALLI, Pavan Santhana Krishna , SEBIRE, Guillaume , HUANG-FU, Chien-Chun , JOHANSSON, Per Johan Mikael
IPC分类号： H04W28/02
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3.发明授权
公开(公告)号：EP3933703B1
公开(公告)日：2024-10-23
申请号：EP21183203.5
申请日：2021-07-01
发明人： HSIAO, Chih-Hsiang , HSU, Chia-Feng
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公开(公告)号：EP4312455B1
公开(公告)日：2024-10-16
申请号：EP23187478.5
申请日：2023-07-25
发明人： LIN, Yuan-Chieh , YANG, Yung-Chun , LIN, Yu-Hsin
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公开(公告)号：EP4439666A2
公开(公告)日：2024-10-02
申请号：EP24165765.9
申请日：2024-03-25
申请人： MediaTek Inc.
发明人： KUO, Che-Hung , YU, Ta-Jen , HUANG, Chi-Hung
IPC分类号： H01L25/10 , H01L25/16 , H01L23/31 , H01L25/065
CPC分类号： H01L25/105 , H01L2225/065120130101 , H01L2225/0656220130101 , H01L2225/102320130101 , H01L2225/104120130101 , H01L2225/105820130101 , H01L2225/103520130101 , H01L23/3128 , H01L24/20 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/16 , H01L25/0657 , H01L25/0655 , H01L25/18 , H01L25/16
摘要： A semiconductor device is provided. The semiconductor device includes a bottom package (300A) and a top package (400). The top package is mounted on the bottom package. At least one portion (400EP) of the top package protrudes from a sidewall of the bottom package. The semiconductor device further includes a passive device mounted on a protruding region of the portion of the top package.
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公开(公告)号：EP4432788A1
公开(公告)日：2024-09-18
申请号：EP24162127.5
申请日：2024-03-07
申请人： MediaTek Inc.
发明人： YI, Tso-Ju , LEE, Chung-Fa
CPC分类号： H05K1/0206 , H05K3/429 , H05K2201/09620130101 , H05K2201/0960920130101 , H05K2201/0963620130101 , H05K2201/0985420130101 , H05K2201/0962720130101 , H05K1/181 , H05K2201/1067420130101 , H05K2201/1071920130101
摘要： An electronic system is provided. The electronic system includes a base and a semiconductor device. The base having a device-attach region includes a build-up layer structure, a vertical interconnect structure and a first through via. The vertical interconnect structure and the first through via are formed passing through the build-up layer structure and located in the device-attach region. The vertical interconnect structure includes a buried via and a blind via electrically coupled to the buried via. The first through via is a straight through via. The semiconductor device is mounted on the device-attach region of the base.
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公开(公告)号：EP4432281A1
公开(公告)日：2024-09-18
申请号：EP24163627.3
申请日：2024-03-14
申请人： MediaTek Inc.
发明人： LIAO, Weinan , HUANG, Jiann-Tseng
IPC分类号： G11C5/14 , G11C7/10 , G11C11/417
CPC分类号： G11C5/14 , G11C7/10 , G11C11/417
摘要： The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry is configured to access the memory array. The control circuit is configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry, wherein the IO circuitry is supplied by a first supply voltage, the control circuit is supplied by at least a second supply voltage different from the first supply voltage.
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公开(公告)号：EP4432280A1
公开(公告)日：2024-09-18
申请号：EP24163622.4
申请日：2024-03-14
申请人： MediaTek Inc.
发明人： LIAO, Weinan , HUANG, Jiann-Tseng
IPC分类号： G11C5/14 , G11C7/12 , G11C11/419
CPC分类号： G11C11/419 , G11C5/145 , G11C7/12
摘要： The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.
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公开(公告)号：EP4432225A1
公开(公告)日：2024-09-18
申请号：EP24164106.7
申请日：2024-03-18
申请人： MediaTek Inc.
发明人： HUANG, Tsung-Shian , WANG, Huei-Long , ZHANG, Yan-Hong , HUANG, Chi-Chiang , WANG, Kuo-Yi , WANG, An-Li , LIN, Chien-Nan
CPC分类号： G06T7/20 , G06T2207/1001620130101 , G06T2207/2022120130101 , H04N7/014 , G06T13/80 , A63F13/50
摘要： A frame interpolation method generates an interpolated frame that is temporally between a first frame and a second frame. A first and a second interpolated frames are generated using motion vectors from a first motion estimator and a second motion estimator, respectively. A weighting map is generated based on indications from the first motion estimator. First pixel locations and second pixel locations in the weighting map are assigned weight values of 1 and 0, respectively. A weighted combination is calculated using the weighting map to produce the interpolated frame output, which includes the first pixel locations from the first interpolated frame and the second pixel locations from the second interpolated frame. The first and the second motion estimators may be an optical flow estimator and the game engine renderer, respectively. Alternatively, the first and the second motion estimators may be the game engine renderer and the optical flow estimator, respectively.
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公开(公告)号：EP3817033B1
公开(公告)日：2024-09-18
申请号：EP20204309.7
申请日：2020-10-28
IPC分类号： H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
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