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    ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS
    2.
    发明授权
    ASYMMETRIC WRITE SCHEME FOR MAGNETIC BIT CELL ELEMENTS 有权

    公开(公告)号：EP2556507B1

    公开(公告)日：2018-09-19

    申请号：EP11713458.5

    申请日：2011-04-05

    申请人： Qualcomm Incorporated

    发明人： ZHU, Xiaochun ,  RAO, Hari M. ,  KIM, Jung Pill ,  KANG, Seung H.

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1693

    摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.

    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON A MIMIC RESISTIVE MEMORY WRITE OPERATION
    3.
    发明公开
    ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON A MIMIC RESISTIVE MEMORY WRITE OPERATION 审中-公开
    基于MIMIC电阻式存储器写操作调整电阻存储器写入驱动器的强度

    公开(公告)号：EP3257046A1

    公开(公告)日：2017-12-20

    申请号：EP16703216.8

    申请日：2016-01-25

    申请人： Qualcomm Incorporated

    发明人： KIM, Taehyun ,  KIM, Jung Pill ,  KIM, Sungryul

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/1677 ,  G11C2013/0078

    摘要： Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.

    READ OPERATION OF CACHE MRAM USING A REFERENCE WORD LINE
    5.
    发明公开
    READ OPERATION OF CACHE MRAM USING A REFERENCE WORD LINE 审中-公开
    使用参考字行阅读高速缓存MRAM的操作

    公开(公告)号：EP3198602A1

    公开(公告)日：2017-08-02

    申请号：EP15767017.5

    申请日：2015-09-09

    申请人： Qualcomm Incorporated

    发明人： KIM, Taehyun ,  KIM, Sungryul ,  KIM, Jung Pill ,  DONG, Xiangyu

    IPC分类号： G11C11/16 ,  G06F12/08

    CPC分类号： G11C11/1673 ,  G11C11/161 ,  G11C11/1693

    摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM) coupled with a tag array, the method comprising: receiving an index and a tag; based on the index, accessing n memory locations in the tag array and for each of the accessed n memory locations comparing data stored therein with the received tag; based on the index, activating a dummy word line in the MRAM; after the activation of the dummy word line, generating a hit signal associated with one of the n memory locations if the comparing indicates a match for said one of the n memory locations; in response to the activation of the dummy word line obtaining a settled reference voltage for reading MRAM bit cells of the MRAM designated by the index; among the MRAM cells designated by the index, reading the MRAM cells having a memory location corresponding to the one of the n-memory location in the tag array providing said hit signal, the reading using the settled reference voltage.

    摘要翻译： 系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。 在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的至少一部分比特来激活伪字线。 基于连接到伪字线的伪单元，开始用于读取第一地址处的MRAM位单元的参考电压的建立过程，并且获得稳定的参考电压。 如果有命中，则基于从第一地址确定的行地址激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

    REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY
    8.
    发明公开
    REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY 审中-公开
    在电阻式存储器实时修正位错误

    公开(公告)号：EP3092649A1

    公开(公告)日：2016-11-16

    申请号：EP14824661.4

    申请日：2014-12-12

    申请人： Qualcomm Incorporated

    发明人： KIM, Taehyun ,  KIM, Sungryul ,  KIM, Jung Pill

    IPC分类号： G11C29/00

    CPC分类号： G06F11/0766 ,  G06F11/1008 ,  G11C29/808 ,  G11C29/814 ,  G11C2029/0411 ,  H03M13/05

    摘要： Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.

    ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS
    10.
    发明公开
    ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS 审中-公开
    FEHLERERKENNUNG UND-KORREKTUR VON EINMALIG PROGRAMMIERBAREN ELEMENTEN

    公开(公告)号：EP2951835A1

    公开(公告)日：2015-12-09

    申请号：EP14703710.5

    申请日：2014-01-22

    申请人： Qualcomm Incorporated

    发明人： KIM, Jung Pill ,  KIM, Taehyun ,  KIM, Sungryul

    IPC分类号： G11C17/02 ,  G06F11/10 ,  G11C17/14 ,  G11C29/02 ,  G11C17/18

    CPC分类号： G06F11/1048 ,  G11C11/16 ,  G11C17/02 ,  G11C17/146 ,  G11C17/18 ,  G11C29/027 ,  G11C2029/4402

    摘要： A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

    摘要翻译： 电路包括第一一次可编程（OTP）元件和第二OTP元件。 电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。 电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。