公开(公告)号：EP2702591B1

公开(公告)日：2015-03-18

申请号：EP12717569.3

申请日：2012-04-23

申请人： SanDisk 3D LLC

发明人： YAN, Tianhong ,  LIU, Tz-yi ,  SCHEUERLEIN, Roy E.

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/73 ,  G11C2213/77

公开(公告)号：EP2109863B1

公开(公告)日：2014-06-18

申请号：EP07869534.3

申请日：2007-12-19

申请人： SanDisk 3D LLC

发明人： YAN, Tianhong ,  FASOLI, Luca G. ,  SCHEUERLEIN, Roy E.

IPC分类号： G11C13/00 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/77

公开(公告)号：EP2422345B1

公开(公告)日：2015-08-12

申请号：EP09793151.3

申请日：2009-09-29

申请人： SanDisk 3D LLC

发明人： YAN, Tianhong ,  FASOLI, Luca

IPC分类号： G11C8/12 ,  G11C13/00

CPC分类号： G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

公开(公告)号：EP2417599A1

公开(公告)日：2012-02-15

申请号：EP10726352.7

申请日：2010-04-02

申请人： Sandisk 3d, Llc

发明人： SAMACHISA, George ,  YAN, Tianhong

IPC分类号： G11C8/14 ,  G11C13/00 ,  G11C7/18 ,  H01L27/24

CPC分类号： G11C13/0007 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

公开(公告)号：EP2342713A1

公开(公告)日：2011-07-13

申请号：EP09737244.5

申请日：2009-09-29

申请人： Sandisk 3d, Llc

发明人： FASOLI, Luca ,  YAN, Tianhong

IPC分类号： G11C7/12 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non- volatile storage element's program operation to complete.

公开(公告)号：EP2321826A1

公开(公告)日：2011-05-18

申请号：EP09790573.1

申请日：2009-07-17

申请人： Sandisk 3D LLC

发明人： YAN, Tianhong ,  FASOLI, Luca

IPC分类号： G11C16/24 ,  G11C16/08

CPC分类号： G11C16/24 ,  G11C13/0028

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

公开(公告)号：EP2304732A1

公开(公告)日：2011-04-06

申请号：EP09771207.9

申请日：2009-06-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  FASOLI, Luca, G. ,  YAN, Tianhong

IPC分类号： G11C13/00 ,  G11C7/22

CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

公开(公告)号：EP2304730A1

公开(公告)日：2011-04-06

申请号：EP09771201.2

申请日：2009-06-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  YAN, Tianhong

IPC分类号： G11C13/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3481 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.

公开(公告)号：EP2304732B1

公开(公告)日：2014-08-20

申请号：EP09771207.9

申请日：2009-06-26

申请人： SanDisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  FASOLI, Luca, G. ,  YAN, Tianhong

IPC分类号： G11C13/00 ,  G11C7/22

CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

公开(公告)号：EP2681738A1

公开(公告)日：2014-01-08

申请号：EP12709997.6

申请日：2012-02-15

申请人： SanDisk 3D LLC

发明人： YAN, Tianhong ,  BALAKRISHNAN, Gopinath ,  LEE, Jeffrey, Koon Yee ,  LIU, Tz-yi

IPC分类号： G11C7/10 ,  G11C7/18 ,  G11C13/00 ,  G11C17/16

CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/18 ,  G11C8/08 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C17/16

摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.